Frequenz, Vol. 66 (2012), pp. 229–238 Copyright © 2012 De Gruyter. DOI 10.1515/freq-2012-0043 Intensity Reflection Coefficient Based Min-Sum Decoding for Low Density Parity Check Codes Mohammad Rakibul Islam, 1; Khandaker Sultan Mahmood, 1 Md. Farhan Tasnim Oshim 1 and Md. Moshiur Rahman Farazi 1 1 Dept. of Electrical and Electronic Engineering, Islamic University of Technology, Board Bazar Originally, also the article Compact LPF Using T-shaped Resonator was published under this DOI. Abstract. Low Density Parity Check Codes (LDPC) give groundbreaking performance which is known to approach Shannon’s limits for sufficiently large block length. Histor- ically and recently, LDPC have been known to give superi- or performance than concatenated coding. In the following paper, a proposal to modify the standard Min-Sum (MS) algorithm for decoding LDPC codes is presented. This is done by introduction of a factor, intensity reflection coeffi- cient (IRC), in the check to bit node updating process. Simu- lation results demonstrate that the proposed algorithms are effective in imparting a better performance in terms of a lower bit error rate (BER) at low to medium signal to noise ratio (SNR) when compared to the traditional MS or Belief Propagation (BP) algorithm while adding a minimum amount of complexity. The proposed algorithm results in a reduced hardware complexity when implemented in VLSI. Keywords. Low-density parity-check codes, min-sum algorithm, belief propagation algorithm, IRC, bit error rate (BER), computational complexity. PACS ® (2010). 84.40.Ua; 89.70.Hj; 02.10.Yn; 78.20.Ci. 1 Introduction Low density parity-check (LDPC) codes were first pro- posed by Gallager in 1963 in [1] and after more than 30 years of research, it was rediscovered by Mackay and Neal [2] and Sipser and Spielman [3]. An extensive research fo- cused on binary LDPC codes have shown to achieve a rate very close to the Shannon’s limit. Such codes have already been considered in communication standards such as digi- tal video broadcasting (DBV-S2), * Corresponding author: Mohammad Rakibul Islam, Dept. of Electrical and Electronic Engineering, Islamic University of Technology, Board Bazar, Gazipur-1704, Dhaka, Bangladesh; E-mail: rakibultowhid@yahoo.com. Received: November 2, 2011. WiFi (802.11n), WiMax (802.16e) and 10 Gigabit Ether- net (10GBASE-T). Codes of various schemes, with a wide range of complexity and fairly effective to highly accurate performance have been achieved. Since rediscovery of Mackay and Neal, several re- searchers have proposed various algorithms which are known to achieve performance with LDPC code near Shan- non limit. M. Fossorier, et al. [5] proposed a new algorithm to reduce the complexity of LDPC code based on belief propagation. Improvement of belief propagation decoding for LDPC code was done by K. Chung, et al. [6], Yuan- Mao Chang, et al. [7], N. Varnica, et al. [8], S. Gounai, et al. [9] and Nedeljko Varnica , et al. [10]. For the Binary Input Additive White Gaussian noise (BIAWGN) channel, an LDPC code of length one million was constructed by Richardson, et al. [11] achieved a bit-error probability of 10 6 less than 0.13 dB away from capacity, surpassing the best (Turbo) codes known hitherto. On that basis, Chung, et al. [12] constructed another LDPC code, which achieved within 0.04 dB of the Shannon limit ( a theoretical capacity of any channel set by Shannon for randomly constructed code) at a bit error rate of 10 6 using a block length of 107. Stochastic Decoding where probabilities are encoded by a Bernoulli sequence was first introduced in [13] for acyclic (16, 8) LDPC code and later improved for capacity- approaching LDPC codes on factor graphs has been done in [14]. In this paper, we present a modification to the standard MS algorithm by introducing a factor  in the algorithm to improve the BER performance and better convergence char- acteristics. Later, we introduce an optimized architecture for the hardware implementation. The various aspects of hardware implementation of the decoding algorithm (num- ber of bits, iterations, architecture) for LDPC codes are con- sidered here. Then we present the hardware modification required to incorporate the new decoding algorithm. The paper is organized as follows: Low density parity check code is discussed in Section 2. Section 3 and 4 re- views standard Belief Propagation (BP) and Min-Sum (MS) decoding algorithms respectively. Our proposed algorithm Min Sum algorithm with Intensity Reflection Coefficient (IRC) is discussed in Section 5. Analysis of the compu- tational complexity is done in Section 6. Simulation re- sults and their interpretation are given in Section 7. Sec- tion 8 deals with the various trade-offs that must be made while implementing a decoder for LDPC codes. Bit node Brought to you by | Universitätsbibliothek der RWTH Aachen Authenticated Download Date | 10/14/15 4:54 PM