IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 5, MAY 2004 271 Vertical p–i–n Polysilicon Diode With Antifuse for Stackable Field-Programmable ROM S. B. Herner, Member, IEEE, A. Bandyopadhyay, Member, IEEE, S. V. Dunton, V. Eckert, J. Gu, K. J. Hsia, S. Hu, C. Jahn, D. Kidwell, M. Konevecki, M. Mahajani, Member, IEEE, K. Park, C. Petti, Member, IEEE, S. R. Radigan, U. Raghuram, J. Vienna, and M. A. Vyvoda Abstract—A field-programmable, stackable memory cell using 0.15- m technology is demonstrated. Vertical polycrystalline sil- icon diodes are stacked on top of one another, with tungsten (with TiN adhesion film) interconnect wires. An SiO antifuse film sep- arates the top of each diode from the TiN–W films. The cell is pro- grammed when sufficient biasing voltage is applied to break down the antifuse, connecting the diode to tungsten. The cell is unpro- grammed when the antifuse is intact. Cell fabrication and perfor- mance are described. Index Terms—Antifuse, breakdown, p–i–n diode, polysilicon, read-only memories (ROMs). I. INTRODUCTION A STACKABLE, field-programmable, read-only memory (ROM) cell using 0.15- m technology is described. The cell can be manufactured entirely with existing silicon-based complementary metal–oxide–semiconductor (CMOS) fabrica- tion tools and materials. With a single cell size of , where F is the minimum feature size, and read/write transistors located underneath arrays of memory cells, an effective density for eight layers of memory bits is or , enabling a very large density of bits per mm of silicon wafer. The cells have an additional advantage over mask ROM technology by enabling the programming of die in the field instead of the fabrication facility. The cell described in this letter is an improvement on similar, previously described cells. By stacking the cells on top of one another, we achieve higher density than single-plane devices [1]. By achieving a larger current difference between programmed and unprogrammed states, we have a larger tolerance for manu- facturing variance. By separating the etch and insulating oxide gap fill of the wiring interconnects from the etch and insulating oxide gap fill of the silicon-based cells, the aspect ratio for gap fill is minimized, enabling scaling of the technology to smaller dimension with minimal change in tool sets [2]–[4]. The cells are shown in schematic in Fig. 1. Vertical polycrystalline sil- icon (polysilicon) diodes are stacked on top of one another, with tungsten (on a TiN adhesion film) interconnect wires in between. The diodes “point” in the opposite direction for each layer, allowing for a simpler read/write circuit architecture, al- lowing the cells to share wiring lines and minimizing the possi- bility of disturb events during programming. An SiO antifuse Manuscript received January 5, 2004; revised February 19, 2004. The review of this letter was arranged by Editor A. Chatterjee. The authors are with the Matrix Semiconductor, Santa Clara, CA 95054 USA. Digital Object Identifier 10.1109/LED.2004.827287 Fig. 1. Schematic of two memory cells with diodes “pointing” in opposite directions. film separates the top of each diode from the tungsten intercon- nect. The cell is unprogrammed when the antifuse is intact. The cell is programmed when sufficient biasing voltage is applied to break down the antifuse, connecting the diode to tungsten. We describe the fabrication and performance of the cells in this letter. II. DEVICE PROCESSING Cells were fabricated on 200–mm silicon wafers. Read/write transistors were fabricated by CMOS processing and insulated from the memory cells above by planarized SiO . The main topic of this letter is the memory cell, and the transistors are fab- ricated from standard processing, thus, we will not discuss tran- sistor fabrication. The transistors applied 10 V to the memory cells for programming and the cells were “read” at 2 V. After transistor fabrication, two layers of etched tungsten films (with TiN adhesion layers) were used to make horizontal and vertical interconnects from the transistors to the memory arrays. Memory cell fabrication and wiring interconnects between the memory cells proceeded after interconnect fabrication from the transistor devices. Wiring layers between memory cells were made by etching 1500- –thick tungsten lines (with a 200- -thick TiN adhesion layer underneath) and depositing SiO by high-density plasma-enhanced chemical vapor depo- sition (HDPCVD) as an insulator between and on top of the etched tungsten lines. Chemical–mechanical polishing (CMP) then removed the oxide from the top of the tungsten lines and planarized the surface. The high removal rate of SiO and low 0741-3106/04$20.00 © 2004 IEEE