An Efficient Voltage Scaling Algorithm for Complex SoCs with Few Number of Voltage Modes Bita Gorjiara, Nader Bagherzadeh, Pai Chou Department of Electrical Engineering and Computer Science University of California, Irvine {bgorjiar, nader, chou}@ece.uci.edu ABSTRACT Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage scaling in each on-chip cores individually, many on-chip voltage regulators must be used. However, the limitations in implementation of on- chip inductors can reduce the efficiency, accuracy and the number of voltage modes generated by regulators. Therefore the future voltage scheduling algorithms must be efficient, even in the presence of few voltage modes; and fast, in order to handle complex applications. Techniques proposed to date, need many fine-grained voltage modes to produce energy efficient results and their quality degrades significantly as the number of modes decreases. This paper presents a new technique called Adaptive Stochastic Gradient Voltage and Task Scheduling (ASG-VTS) that quickly generates very energy efficient results irrespective of the number of available voltage modes. The results of comparing our algorithm to the most efficient approaches (RVS and EE-GLSA) show that in the presence of only four valid modes, the ASG-VTS saves up to 26% and 33% more energy. On the other hand, other approaches require at least ten modes to reach the same level of energy saving that ASG-VTS achieves with only four modes. Therefore our algorithm can also be used to explore and minimize the number of required voltage levels in the system. Categories and Subject Descriptors C.3 [Special-purpose and application-based systems]: Real-time and embedded systems General Terms: Algorithms and Design. Keywords: Dynamic Voltage Scaling (DVS), scheduling, power management, optimization, stochastic gradient search, heterogeneous systems, and multi-processor systems. 1 INTRODUCTION Design of future embedded systems becomes more challenging due to the increasing demand for larger high performance applications. Scaling the technology to deep submicron allows placement of hundreds or even thousands of processing cores on a single chip. Managing dynamic and leakage power at that scale poses a major challenge for future designs. The fact that dynamic power and static power have quadratic and exponential relationship to the supply voltage respectively [22] necessitates voltage scaling in components and subcomponents of a chip. To allow dynamic voltage scaling in each of the on-chip cores, it is required to have many on-chip voltage regulators that can provide DVS modes as well as shutdown mode. Currently on-chip regulators cannot provide shutdown mode, and have low efficiency due to the low accuracy of on-chip inductors [5]. Such limitations can lead to significant reduction in the number and accuracy of the available voltage levels especially in deep submicron and SoCs with many processing cores. Design of low power embedded systems is usually an iterative process that explores different resource allocations and task mappings to meet performance, power and cost constraints. For each of the system configuration generated during design space exploration, the application tasks are scheduled on the mapped resources (task scheduling) to meet real-time deadlines. The available slack intervals in the schedule are utilized by voltage (and frequency) scaling algorithm to reduce energy consumption. Figure 1 shows the flow of a typical system design space exploration process [4] that uses two nested genetic algorithms (GAs) to generate various system configurations with different resource allocations and task mappings. The task scheduling and voltage scaling algorithms are in the inner-most loop of this iterative process and therefore must have a very low algorithm complexity in order to handle large applications with too many tasks. Figure 1. The Design Space Exploration Process proposed in [4] So far, the algorithms proposed for voltage scheduling either are not very energy efficient, or have a high order of complexity, and/or need many fine-grained supply voltage levels (voltage modes) to generate efficient results. Some of the approaches even formulate the problem for continuous voltage values. If few voltage modes are provided in a system, then they map the generated continuous solution to a valid mode with a relatively high energy penalty. This paper presents a new technique called Adaptive Stochastic Gradient Voltage and Task Scheduling (ASG-VTS) that selects voltage modes for a set of dependent tasks mapped to a heterogeneous system so that the energy consumption is optimized and no real-time deadline is violated. Our algorithm has a low complexity and produces highly energy efficient results even in the presence of few voltage modes. To achieve high energy efficiency, we have developed a discrete stochastic heuristic for slack distribution that is combined with iterative adjustment of task ordering. Whenever a local minimum is found, ASG-VTS stochastically re-claims some of the assigned slack time (slack recovery), and restarts the slack distribution process in order to search a broader space. Our experimental results show that our Evaluation / Selection Task and Voltage Scheduler Application Specification Allocation Resource Library Mapping Evaluation / Selection A GA GA B Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ISLPED’04, August 9–11, 2004, Newport Beach, California, USA. Copyright 2004 ACM 1-58113-929-2/04/0008…$5.00. 14.2 381