Transformation of a synthesizable subset of ANSI C code into behavioral SystemC code Piotr Dziurzanski, Vladimir Beletskyy Faculty of Computer Science & Information Systems, Technical University of Szczecin, ul. Zolnierska 49, 71-210 Szczecin, Poland e-mail: pdziurzanski@wi.ps.pl, bielecki@man.szczecin.pl Abstract: In this paper, there is a preliminary description of a system under development for translating codes written in ANSI C into behavioral SystemC codes. The limitation of the translable structures of ANSI C are described and implementation details are stressed. Key words: Higl level synthesis, synthesizable subset, ANSI C, System C 1. INTRODUCTION Different hardware description languages (HDLs) are used as input to behavioral synthesis. The most commonly used are VHDL and Verilog, but since designers often write system level models using programming languages, application of software languages are of mounting popularity. Applying software languages makes easier performing SW/HW cosynthesis, which accelerates the design process and improves the flexibility of the software/hardware migration. Moreover, the system performance estimation and verification of the functional correctness is easier, as software languages offer fast simulation and a sufficient amount of legacy code and libraries which facilitate the task of system modelling. To implement parts of the design modelled in C/C++ in hardware using synthesis tools, designers must translate these parts into a synthesizable subset of a HDL, which then is synthesized into a logic netlist. A leadership of ANSI C/C++ in the field of software languages contributes to a large number of HDLs based on these languages, for example SystemC, Cynapps, Accellera, and SpecC. This choice makes rewriting the C/C++ code into an equivalent HDL description less time consuming and less error prone that results in a shorter time to market and higher quality [4].