Achieving Highly Reliable Wireless Communication System Design Using A Model-based RTL Design * Department of Computer Science and Electronics Graduate School of Computer Science and System Engineering Kyushu Institute of Technology Kawazu 680-4, Iizuka-shi, Fukuoka-ken, JAPAN Email: wasyafei (nagao, nishijo, teramoto, kurosaki, ochi) @dsp.cse.kyutech.ac.jp ** Radrix. Co. Ltd. http://www.radrix.com Wahyul Amien SYAFEI*, Yuhei NAGAO*, Kunitoshi NISHIJO*, Akihiro TERAMOTO*, Masayuki KUROSAKI*, and Hiroshi OCHI** FPGA board, Chip maker, etc. FPGA board, Chip maker, etc. Proposed Method Conventional Method RTL Design (HDL) Architecture Design Long time hard work High possibility human error Evaluation of mathematical model absorbs more resources, yield to … unreliable system design more time to consider in high level system design Easy looking simulator Easy to match with desired target Instead of writing the HDL codes, we propose A Model-based RTL Design in the trip to FPGA board Avoid human error reliable system design Easy micro adjustment Synplify ® DSP MATLAB ® / Simulink ® Synplify ® Pro,ISE ® ,Quartus2 ® Difficulties to change the spec. Hard micro adjustment IEEE Globecom 2007. Washington DC. Poster Session. Wednesday, Nov, 28, 2007 • 12:00 am – 6:00 pm. Dept. of Computer Science & Electronics. Kyushu Institute of Technology. Japan High Level Design Verification A Model-based RTL Design Logic Synthesis