Computers & Operations Research 35 (2008) 1084 – 1098 www.elsevier.com/locate/cor A hybrid genetic heuristic for scheduling parallel batch processing machines with arbitrary job sizes Ali Husseinzadeh Kashan, Behrooz Karimi ∗ , Masoud Jenabi Department of Industrial Engineering, Amirkabir University of Technology, 424 Hafez Ave., Tehran 15916-34311, Iran Available online 17 August 2006 Abstract This paper investigates the scheduling problem of parallel identical batch processing machines in which each machine can process a group of jobs simultaneously as a batch. Each job is characterized by its size and processing time. The processing time of a batch is given by the longest processing time among all jobs in the batch. Based on developing heuristic approaches, we proposed a hybrid genetic heuristic (HGH) to minimize makespan objective. To verify the performance of our algorithm, comparisons are made through using a simulated annealing (SA) approach addressed in the literature as a comparator algorithm. Computational experiments reveal that affording the knowledge of problem through using heuristic procedures, gives HGH the ability of finding optimal or near optimal solutions in a reasonable time.  2006 Elsevier Ltd. All rights reserved. Keywords: Scheduling; Parallel batch processing machines; Genetic algorithm; Simulated annealing 1. Introduction This paper addresses the problem of scheduling n jobs on m identical parallel batch processing machines. A batch processing machine is capable to accommodate a group of jobs simultaneously. Once processing of a batch is initiated, it cannot be interrupted and other jobs cannot be introduced into the machine until processing is completed. With each job i we shall associate an arbitrary size s i and an arbitrary processing time p i . Each batch processing machine has a capacity B, so the sum of job sizes in each batch must be less than or equal to B. We assume that no job has a size exceeding the machine capacity and it cannot be split across batches. This research is motivated by burn-in operation in semiconductor manufacturing [1]. The purpose of burn-in operation is to test the integrated circuits by subjecting them to thermal stress for an extended period. The burn-in oven has a limited capacity and sub-grouping the boards holding the circuits in to batches would be inevitable. So, using all or as much available space in the processor maximizes efficiency. The processing times of burn-in operations are generally longer compared to those of other testing operations, so the burn-in operations constitute a bottleneck in the final testing operation and optimal scheduling of the burn-in operations is of great concern in productivity and on-time delivery management. In scheduling problems, makespan (C max ) is equivalent to the completion time of the last job leaving the system. The small C max usually implies a high utilization. The utilization for bottleneck station is closely related to throughput ∗ Corresponding author. Tel.: +98 21 66413034; fax: +98 21 66413025. E-mail address: b.karimi@aut.ac.ir (B. Karimi). 0305-0548/$ - see front matter  2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.cor.2006.07.005