Addressable F ailure S ite T est S tructures (AFS-TS) for Process Development and Optimization Kelvin Yih-Yuh Doong 1,2 , Sunnys Hsieh 1 , Sheng-Che Lin 1 , Binson Shen 1 , Wang Chien-Jung Yen-Hen Ho 1 , Jye-Yen Cheng 1 , Yeu-Haw Yang 1 , Koji Miyamoto 3 , and Charles Ching-Hsiang Hsu 2 1 Worldwide Semiconductor Manufacturing Corp., Shinchu, Taiwan TEL: 886-3-567-8888 ext. 2151, FAX: 886-3-566-2040, Email: kelvind@wsmc.com.tw N.. 25, Li-shin Road, Science-based Industrial Park, Hsinchu, Taiwan, Post-code: 300 2 Microelectronics Laboratory, Semiconductor Technology & Application Research (STAR) Group, Department of Electrical Engineering, National Tsing-Hua University, R.O.C. 3 MOS Process Integration technology Department Micro & Custom LSI Division, Toshiba Corporation, Yokohama, Japan Abstract-Two types of addressable failure site test structures are developed. In-house program is coded to extract the electrical information and simulate the failure mode. A complete set of test structure modules for 0.25 um logic backend of line process is implemented in a test chip of 22x6.6 mm 2 . By using the novel test structure, the yield analysis and defect tracking of BEOL process development as well as low-k Fluorinated SiO 2 (FSG) process optimization are demonstrated. INTRODUCTION THE TEST structure of process integration has shown its necessity and importance not only in the field of yield monitor of integrated circuit production line but also at the early regime of process development. The process development and control strategy by using test structure had been profiled and the expert system of analysis was designed by Lukaszek, W. and etc[1]. The test vehicle of static random access memory (SRAM) is typically used for high performance micro-processor process development and in-line process monitor[2, 3]. The force-sense type of test structures with multiplexers had been implemented to reduce chip pad counts as well as increase the testing speed and effective area of test structures[4, 5]. A novel checkerboard test structures without active devices was used to detect defect information and a generic algorithm solve the ambiguity induced by multi-defect inside a test chip[6, 7]. However, the area of probe pad is relatively larger than real chip design, which means, in order to get larger capture rate of yield killer, we have to increase the total chip area[1]. Due to the inherent purpose of process monitoring test vehicle is for process monitoring and control of volume production line, most of test structures are not suitable for short-loop process[2, 3]. For the other test vehicles, either the testing methods is required the digital tester, which are not compatible with in-line process[5, 6], or the multi-fault of the test chip will be derived from the design methodology and defect identification algorithm[6, 7]. Hence, we propose a generic test structure system for all kinds of semiconductor products, called as addressable failure site test structures (AFS-TS) [8, 9]. Besides the parametric extraction of test structures such as P/NMOSFET, reliability, overlay measurement, Kelvin 4-point structures, Van der Pauw and etc., the open- circuit and short-circuit of test structures for conductive layers are the major and important items of yield measurements. In this work, we will present two types of addressable failure site test structure (AFS-TS) for the yield measurement of conductive layers. The simulation was performed to extract electrical characteristic of AFS-TS and detect the single/multi faults inside test chip. The guideline of test structure design is discussed, and followed as system implementation of in-line process. Finally, the systemic design procedure was verified by implementing the 0.25 um logic BEOL process, and process optimization of low-k Fluorinated SiO 2 (FSG) was illustrated. DESIGN METHODOLOGY A. Terminology and Modeling For the convenience sake on model description, some graphic terminology has been adopted to model the geometry of layout objects inside a test structure[10]. The nodes (N = { N 1 , N 2 , N 3 ¡ , N k }) stand for the measurement points with conductive layout objects (conductive unit [CU]) like comb or meandering lines. The line (L) describes the measurement path between two measuring pads, either short circuit check (SCC) or open circuit check (OCC). L = { L ij , i, j = 1, 2, 3 ¡ , k (a) if i 1 j, the L ij means Short Circuit Check Unit (SCCU); (b) If i = j, the L ij means Open Circuit Check Unit (OCCU); } The whole test structure is noted by G = (N, L). Figure 1 shows the schematic layouts & their geometry graphs of typical test structures. The compound test structure of comb and serpentine for conductive layers is shown in Fig. 1(a-1). L= { L 12 , L 13 , L 24 , L 34 } are SCCUs and L = { L 11¡ , L 44¡ } are OCCUs, which of corresponding geometry graph is in Fig. 1(a-2). The serpentine test structure of multi-nodes for conductive layers is shown in Fig. 1(b-1). L = { L ij , i, j = 1, 2, 3, 4, 5 i 1 j }, are OCCUs, which of corresponding geometry graph is in Fig. 1(b-2). The serpentine test structure for inter-connect layers is shown in Fig. 1(c-1). L = { L 12 , L 13 , L 24 , L 34 } are SCCUs and L = { L 11¡ , L 22¡ } are OCCUs, which of corresponding geometry graph is in Fig. 1(c-2) and Fig. 1(c-3).