IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 6, NO. 4, APRIL 2016 653 Nondestructive Monitoring of Die Warpage in Encapsulated Chip Packages Ankit Bose, Rajani K Vijayaraghavan, Aidan Cowley, Vladimir Cherman, Olalla Varela Pedreira, Brian K. Tanner, Andreas N. Danilewsky, Ingrid De Wolf, Senior Member, IEEE, and Patrick J. McNally, Senior Member, IEEE Abstract—We describe an X-ray diffraction imaging technique for nondestructive, in situ measurement of die warpage in encapsulated chip packages at acquisition speeds approaching real time. The results were validated on a series of samples with known inbuilt convex die warpage, and the measurement of wafer bow was compared with the results obtained by optical profilometry. We use the technique to demonstrate the impact of elevated temperature on a commercially sourced micro quad flat nonlead chip package and show that the strain becomes locked in at a temperature between 94 °C and 120 °C. Using synchrotron radiation at the Diamond Light Source, warpage maps for the entire 2.2 mm × 2.4 mm × 150-μm Si die were acquired in 50 s, and individual line scans in times as short as 500 ms. Index Terms— Components, integrated circuit packaging, manufacturing technology, packaging, semiconductor device manufacture, semiconductor device packaging. I. I NTRODUCTION W E HAVE now entered an era where integrated chip manufacturing must encompass the development of complex chip systems capable of diverse functionality. The Manuscript received October 8, 2015; revised January 25, 2016; accepted February 1, 2016. Date of publication March 2, 2016; date of current version April 1, 2016. This work was supported in part by the European Community’s Seventh Framework Programme (FP7/2007-2013) through the CALIPSO Project under Grant 312284, in part by the Irish Higher Education Authority within the INSPIRE Programme through the Irish Government Programme for Research in Third Level Institutions, Cycle 5, National Development Plan 2007-2013 and the European Union/European Regional Development Fund/European Social Fund, in part by Dublin City University, Science Foun- dation Ireland’s within the Strategic Research Cluster Programme through the Precision Project under Grant 08/SRC/I1411. Recommended for publication by Associate Editor I. C. Ume upon evaluation of reviewers’ comments. A. Bose, R. K. Vijayaraghavan, and P. J. McNally are with the School of Electronic Engineering, Dublin City University, Dublin 9, Ireland (e-mail: ankit.bose2@mail.dcu.ie; rajani.vijayaraghavan@dcu.ie; patrick.mcnally@dcu.ie). A. Cowley was with the School of Electronic Engineering, Dublin City University, Dublin 9, Ireland. He is now with the European Space Agency, European Astronaut Centre, Cologne 51147, Germany (e-mail: aidan.cowley@esa.int). V. Cherman and O. Varela Pedreira are with imec, Leuven 3001, Belgium (e-mail: vladimir.cherman@imec.be; olalla.varelapedreira@imec.be). B. K. Tanner is with the Department of Physics, Durham University, Durham DH1 3LE, U.K. (e-mail: b.k.tanner@durham.ac.uk). A. N. Danilewsky is with the Crystallography Institute and the Institut für Geo- und Umweltnaturwissenschaften, Albert Ludwigs University of Freiburg, Freiburg im Breisgau 79085, Germany (e-mail: a.danilewsky@krist. uni-freiburg.de). I. De Wolf is with imec, Leuven 3001, Belgium, and also with the Faculty of Engineering, Katholieke Universiteit Leuven, Leuven 3000, Belgium (e-mail: ingrid.dewolf@imec.be). This paper has supplementary downloadable material available at http://ieeexplore.ieee.org., provided by the author. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCPMT.2016.2527060 application areas themselves are vast and include areas such as the automotive, energy, health care, Internet of Things, and security sectors [1]. The general nomenclature of More than Moore manufacturing is often used to capture this increasing diversity of function and application [1], [2]. Key enabling technologies for the requisite advanced packaging include the processing of semiconductor die that are becoming much thinner (e.g., die thickness approximately 25–100 μm), and many packages include multiply stacked silicon die. The packages that encapsulate the die are themselves becoming increasingly thinner, and there is a tradeoff between the thickness of constituent package layers and their rigidity, which often leads to reliability problems [3]. Such advanced packages include system-in-package, system-on-chip, micro- electromechanical systems, and 3-D integrated circuits (3-D ICs) [1]–[8]. The development of a nondestructive, in situ metrology that can analyze the warpage/bow of the semiconductor die inside these packages is particularly challenging. It would be a real advantage if the metrology is also capable of real- time measurement of the die warpage during anneal processes, particularly as a means of pinpointing the impact of crucial process steps on the development or amelioration of these warpage problems. A recent review [3] examined the range of metrology tools available for the characterization of ultrathin wafer and die quality, and these included techniques such as optical and electron microscopy, optical and mechanical profilometry, high-resolution X-ray diffraction, micro-Raman spectroscopy, scanning infrared depolarization, atomic force microscopy, and stress bending tests. However, none of these techniques is capable of in situ and nondestructive measure- ment of the nature and scale of wafer or die bow/warpage across an entire die. Many of the techniques are destructive and those that are nondestructive tend to measure the package bow, which, crucially, is not the same as the wafer/die bow. Furthermore, there is no consensus as to how one could implement an in situ analysis of die warpage when the package is undergoing thermal processing steps or is otherwise at an elevated temperature. Over the past few years, we have been developing novel B-spline X-ray diffraction imaging (B-XRDI) tech- niques, which can map lattice misorientation to produce in situ die warpage maps from X-ray diffraction data/images of the semiconductor die inside fully encapsulated ball grid array (BGA) and quad flat nonlead (QFN) packages [9]–[14]. In the first instance, the technique has relied on the use of synchrotron X-ray sources, as these provide the great- 2156-3950 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.