478 • 2017 IEEE International Solid-State Circuits Conference ISSCC 2017 / SESSION 28 / HYBRID ADCS / 28.7 28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm CMOS with Digital Amplifier Technique Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura Toshiba, Kawasaki, Japan Wireless standards, e.g. 802.11ac Wave 2 and 802.11ax draft, aim to boost user throughput to cope with growing data traffic. High-speed (f s >100MS/s) and high- resolution (ENOB>9.5b) ADCs are essential for leading-edge wireless SoCs, given the bandwidth and PAPR specifications. Also, low power dissipation (FoM<20fJ/conv) is crucial for mobile applications. A number of pipelined-SAR ADCs have been presented which satisfy these design targets [1-3]. However, in deep submicron CMOS, design of a high DC-gain opamp for the MDAC is a serious obstacle due to reduced intrinsic transistor gain and sub-1V supply voltage. Hence, all designs utilize digital calibration to counter gain error and tolerate the use of a low-gain amplifier. Calibration times of at least several tens of ms are required, resulting in lengthy start-up times and reduced SoC power efficiency. Moreover, such calibration cannot track sudden supply voltage variations and suppressing such fluctuations with bypass capacitors significantly impacts chip cost [1-2]. Furthermore, amplifier non-linearity remains unsolved; with lower supply voltages, the limited amplifier swing tightens SAR noise requirements. We propose a calibration-free 0.7V 12b 160MS/s pipelined-SAR ADC with digital amplifier (DA) technique. The DA cancels out all errors of the low-gain amplifier by feedback based on successive approximation (SA). Errors are detected by judging virtual ground polarity and canceled out by a C-DAC. The amplification accuracy is determined by the C-DAC LSB step and irrelevant to the intrinsic gain, and thus suitable for scaled CMOS. Without any calibration, an SNDR of 61.1dB is achieved at the Nyquist frequency, consequently achieving an FoM of 12.8fJ/conv. Figure 28.7.1 shows the DA concept and its implementation in a 2.5b MDAC. The DA achieves high effective loop-gain in scaled CMOS to realize a calibration-free ADC. Foremost, the DA-based MDAC operation is divided into 2 phases: opamp and DA. During opamp phase, φ OP , the low-gain opamp is connected to the MDAC output. However, an error occurs owing to the non-ideal effects of the opamp (e.g., gain error, non-linearity, incomplete settling, power supply noise, and thermal noise). Importantly, all these effects can be detected from the virtual ground condition (V x ) and by converging V x to zero, all non-ideal effects can be removed. During DA phase, the virtual ground is forced to zero by carrying out feedback based on successive approximation (SA), utilizing a clocked comparator and a C-DAC. The comparator judges the polarity of V x and the C-DAC connected at the MDAC output is controlled so that V x will converge to 0. After n cycles of DA operation, V out will always converge to the ideal V out with an error range of the C-DAC LSB voltage, V CDACLSB . A significant feature of the DA is that its gain error can be determined by the step size of V CDACLSB and is irrelevant to intrinsic gain. V CDACLSB can be halved by increasing DA resolution by 1b, which is equivalent to improving the opamp loop- gain by 6dB. Our opamp is designed in 28nm CMOS and can achieve a loop gain of only 20dB in the worst conditions, contrary to the >60dB loop-gain required for the ADC target performance. From the given DA principal shown in the right- top of Fig. 28.7.1, the opamp loop-gain, A’ is boosted to the effective loop-gain of 20dB+6dB×7b=62dB, if a 7b DA is utilized. As a result, over cubic enhancement of the opamp loop-gain is achieved with the DA, while correlated level-shifting (CLS) technique enhancements are limited to a square [4]. Moreover, in the conventional designs, all errors excluding gain error had to be suppressed to an equivalent level to the gain error. With DA, these errors, including settling error, can be tolerated as long as it does not exceed the C-DAC full-scale (V CDACLSB ×2 n ). Therefore, DA can save significant power by relaxing opamp settling. In this design, the budget of all errors was chosen to maximize the ADC power-efficiency and as a result, an 8b DA was chosen. The DA comparator noise is designed to be 160μVrms at typical conditions, similar to 12b SAR ADC noise requirements with the same signal swings. The DA technique has an excellent process- portability since the opamp performance variation can be easily compensated by re-configuring the DA resolution. Moreover, the DA circuitry is mostly digital and greatly improves its performance with process scaling. Figure 28.7.2 shows the block diagram and timing chart of the two-way interleaved pipelined-SAR ADC. The 12b results are obtained by the 1 st -stage 2.5b MDAC and the 2 nd -stage 10b fine SAR ADC (FSAR) with the proposed look-ahead SAR (LA SAR). The FSAR with 2b redundancy adapts subrange SAR techniques [5] to improve the power-efficiency and on top of that, the proposed LA SAR foresees and acquires 3b MSB from the half-way DA amplification results. The ADC operation is asynchronous: when the channel sampling clock (φ s ) falls, opamp phase of the MDAC is carried out and then the DA operation consisting of 8 SA cycles starts. After the 3rd cycle, the 3b LA SAR is activated, which samples halfway DA amplification results and the LA SAR conversion is carried out simultaneously with the DA operation. The 3b MSB results are resolved beforehand by the LA SAR and passed to the FSAR and a total speed improvement of 25% is achieved. The amplification error, noise and offset contained in the LA SAR results are compensated by the FSAR redundancy. Therefore, LA SAR requirements are greatly relaxed and its area is only 5% of FSAR. Furthermore, the most power-consuming MSB transitions are done by a small C-DAC, which results in 30% DAC switching power savings. A proposed time-based current source (TBCS) is utilized for opamp reference current generation to further enhance PVT robustness. Assuring opamp speed throughout PVT variations is challenging since the reference current (I REF ) also varies with PVT, dominated by poly-resistor drifts (typically ±20%). Figure 28.7.3 shows the concept and schematic of the TBCS. When a DLL locks at a constant delay, the settled current can be used as a PVT-robust reference since the delay of the current-starved inverter is mostly determined by the current and the load capacitance. The DLL locks by configuring the R-DAC, and after locking, chattering is prevented by utilizing a 2b TDC and applying hysteresis to the R-DAC configuration. According to simulation, the I REF variation through worst PVT was ±8.5%, which is almost halved when compared to poly-resistor variation. Unlike BGR circuits, TBCS is highly process-scalable; the occupied area is only 800μm 2 . Moreover, the phase outputs of the delay line are used to generate pulse φ OP and to terminate lingering DA operation to ensure FSAR completion. The TBCS can be reused as a multi-phase clock generator. The ADC is fabricated in 28nm CMOS and occupies 0.097mm 2 (Fig. 28.7.7), including the bypass capacitor of only 70pF. Reference buffers are not required and the ADC operates with a single 0.7V supply. Without any calibration for both channel ADCs and interleaving blocks, the ADC achieves an SNDR of 61.1dB with 160MS/s Nyquist input, and a power consumption of only 1.9mW. Figure 28.7.4 shows the ADC characteristics of 3 randomly chosen samples. To confirm the robustness of the calibration-free ADC, a temperature variation from -40 to 125°C was applied, and all samples achieved an SNDR>59.5dB with 160MS/s operation. Moreover, the SNDR is flat over varied f s and f in . Figure 28.7.5 shows the spectrum of the ADC and DNL/INL, respectively. Figure 28.7.6 compares the ADC performance with state-of-the-art high-speed pipelined-SAR and pipelined ADCs [1-2,6]. The proposed ADC achieves an FoM of 12.8fJ/conv without calibration, which is a 3× improvement compared to the conventional calibration-free pipelined/pipelined-SAR ADCs with fs>50MS/s and SNDR>56dB [3]. References: [1] B. Verbruggen, et al., “A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS,” IEEE Symp. VLSI Circuits, pp. 1-2, June 2014. [2] Y. Zhou, et al., “A 12 bit 160 MS/s two-step SAR ADC with background bit- weight calibration using a time-domain proximity detector,” IEEE JSSC, vol. 50, no. 4, pp. 920–931, Apr. 2015. [3] B. Murmann, "ADC Performance Survey 1997-2016". Accessed on 13 Nov. 2016, <http://web.stanford.edu/~murmann/adcsurvey.html>. [4] B.R. Gregoire, U.K. Moon, “An Over-60dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp with 30dB Loop Gain,” ISSCC, pp. 540- 541, Feb. 2008. [5] H.-Y. Tai, et al., “A 0.85fJ/conversion-step 10b 200kS/s Subranging SAR ADC in 40nm CMOS,” ISSCC, pp.196-197, Feb. 2014. [6] Y. Chai, J. Wu, “A 5.37mW 10b 200MS/s Dual-Path Pipelined ADC,” ISSCC, pp.462-463, Feb. 2012. 978-1-5090-3758-2/17/$31.00 ©2017 IEEE