This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON ELECTRON DEVICES 1 A DC Method to Extract Mobility Degradation and Series Resistance of Multifinger Microwave MOSFETs Andrea Sucre-González, Fabián Zárate-Rincón, Student Member, IEEE, Adelmo Ortiz-Conde, Senior Member, IEEE , Reydezel Torres-Torres, Senior Member, IEEE , Francisco J. García-Sánchez, Senior Member, IEEE , Juan Muci, and Roberto S. Murphy-Arteaga, Senior Member, IEEE Abstract— Extrinsic parasitic series resistance and mobility degradation are two important parameters limiting the per- formance of multifinger microwave MOSFETs. In this paper, we present a method to extract these parameters from measured drain-voltage versus gate-voltage characteristics at given constant values of drain current. Measured data of multifinger microwave MOSFETs are used to test and verify the developed method. The method requires only simple dc measurements on a single test device. Index Terms— Mobility degradation, MOSFET model parame- ter extraction, multifinger microwave MOSFETs, parasitic series resistance. I. I NTRODUCTION T HE layout of RF-MOSFETs is carefully designed to reduce the effect of the extrinsic parasitic series resis- tances, which may considerably impact the performance of the device at high frequencies. Thus, several methodologies have been proposed to characterize this effect in different geometries and bias conditions [1]–[6]. In a previous work on RF-MOSFETs [7], [8], the effect of using multifingering of the gate electrode on the drain and source parasitic resis- tances was analyzed. In that work, S-parameter measurements were used to carry out the corresponding parameter extrac- tion for different geometries. S-parameter measurement-based characterization methodologies allow for a full and accurate description of MOSFETs under different bias conditions. However, the determination of parasitic series resistances and the assessment of the corresponding effect become difficult, as the gate-to-source voltage considerably becomes higher than the threshold voltage [9]. This is due to the fact that under such a condition, the device’s output impedance is very Manuscript received November 24, 2015; revised February 17, 2016; accepted March 1, 2016. The review of this paper was arranged by Editor P. J. Fay. A. Sucre-González, A. Ortiz-Conde, F. J. García-Sánchez, and J. Muci are with the Department of Electronics, Universidad Simón Bolívar, Caracas 1080A, Venezuela (e-mail: andresucre88@gmail.com; ortizc@ ieee.org; fgarcia@ieee.org; jmuci@usb.ve). F. Zárate-Rincón, R. Torres-Torres, and R. S. Murphy-Arteaga are with the Department of Electronics, Instituto Nacional de Astrofísica, Óptica y Electrónica, Puebla 72840, Mexico (e-mail: fabian_zar@inaoep.mx; reydezel@inaoep.mx; rmurphy@inaoep.mx). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2016.2538778 small compared with the impedance reference value at which the S-parameters are typically measured (i.e., 50 ). Thus, when processing S-parameters for separating the contribution of the channel source and drain resistances from the output impedance, a high level of uncertainty is observed at gate voltages approaching the maximum value allowed by the technology. Notwithstanding this fact, the contribution of the series resistance at this voltage level must be quantified to either incorporate the corresponding effect into a small-signal model or characterize a particular device’s structure and layout at this normal operation condition. On the other hand, dc measurements have also been used to extract MOSFET models’ parameters. In this case, how- ever, the presence of source-and-drain series resistance and mobility degradation has a similar effect on the device’s I D (V GS ) transfer characteristics and, therefore, is difficult to separate. For this reason, several procedures have been reported to get around this obstacle [10]–[33]. For instance, nonlinear optimization techniques were proposed to extract the series resistance [10], [32]. In [13], a method to extract the total series resistance was presented for fully depleted Silicon-On-Insulator MOSFETs operating in the saturation region. In [17], a clever method was proposed to extract the series resistance with bias conditions that keep the channel carrier mobility constant. Indirect fit- ting of the source-to-drain resistance was also proposed in [20]–[22]. A procedure based on the integration of the total series resistance with respect to gate bias was proposed in [19]. Several proposals have been put forward recently. Among them are a novel test structure [30], a novel RF method [31], and a capacitance-based method [29]. Possible asymmetry between the drain-and-source resis- tance, which was first independently analyzed in [34]–[36], is a factor to be considered in modern devices [37], [38] but will not be discussed here for the sake of conciseness. For multifingered devices, the source and drain resistances are strongly dependent on the layout scheme used (number of fingers and gate electrode’s general shape). Fortunately, the method presented here has the advantage of allowing parameter extraction to a single device. Thus, the impact of the device layout, access resistance, and other variations can be systematically analyzed using our present proposal. 0018-9383 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.