International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 04 Issue: 05 | May -2017 www.irjet.net p-ISSN: 2395-0072 © 2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 3568 RTL Synthesis and Analysis of Digital Code Lock System Sabyasachi Mukhopadhyay 1 , Sandeep Singh 2 1 Assistant Professor, Dept. of ECE, SET, Sharda University, Greater Noida, UP, India. 2 Assistant Professor, Dept. of ECE, SET, Sharda University, Greater Noida, UP, India. ---------------------------------------------------------------------***--------------------------------------------------------------------- Abstract - Security is a prime concern in our day-to-day life. An access control for locks forms a vital link in a security chain. The work which has been carried out in this paper presents the design of a keyless coded lock system. The operation is conducted by entering a combination of binary code to access the lock. If the correct sequence is detected, then it will unlock the lock otherwise it will remain locked. RTL synthesis is carried out using in ISE Design suit 14.1. ISim simulator is used for the functional verification. Key Words: FSM, Sequence detector, HDL, RTL synthesis, Behavioral model. 1. INTRODUCTION In data communication network, any digital data is transmitted in the form of bit at a very high speed. Such movement of data is commonly called bit stream. One bit in any bit stream looks alike to many other bits. It is of utmost importance that any receiver can identify important information in a bit stream [1]. Digital code based lock system is basically a security system which allows any user to unlock the lock by entering a correct binary code to unlock the lock. The objective of the system is to provide enhanced security features. It also eliminates the possibility of the lock being broken. It is a key less security system where the owner only has to know the proper code to unlock the system [4]. The lock which is generally used in electronic safe is actually a code lock based system. The code which is being used may be numeric or alpha numeric [3]. In this work the code being used is binary in nature. Finite State Machines (FSM) are generally sequential logic circuits. Such models are of high importance to realize certain types of systems, particularly those whose tasks form a well-defined sequence. The major applications of FSM are to implement operations that are performed in a sequence of steps [5]. FSMs are broadly classified as Mealy and Moore machines. The system has been presented in this paper is of Mealy type as the output depends on the state of the memory unit as well as on the present combination of the input. The system has been coded with HDL. The RTL synthesis and functional verification has been carried out using ISim simulator. The rest of the paper is organized as follows. In section 2, the design flow has been discussed. In section 3, RTL synthesis has been carried out. After that, in section 4, the simulation results have been shown and in section 5, the conclusion has been made. 2. DESIGN FLOW The operation procedure of the code based digital lock system is based on the detection of a specific pattern given in binary number. In order to unlock the system one has to enter the correct pattern via the keypad module. This kind of lock can avoid the problems caused by the copying of keys. On the premise that its safety is high, it’s another feature without key is getting more and more favor of people. There are great varieties of digital code locks. Generally speaking, they can be classified into score of type, such as electronic lock, fingerprint lock, card lock biological lock, etc. The code which has been used in this design is DzͳͲͳͳͲdz to unlock the system. The inputs to the system are considered as clock, reset and x. The corresponding output is y which indicates the locking and unlocking status. Five states of the memory element have been considered. As the system is consists of five states hence three flip-flops of D-type is utilized for the implementation of the system. Each of the states is tested and a state transition is considered whenever there is a correct sequence of bit is received. The unlocking is considered by making the output bit as Dzͳdz as the correct pattern is fed in the input. Since overlapping is permitted hence the design consideration looks after the last two bits of the sequence to get another desired code. The state transition of the system is tabulated in Table 1. After the system realization it has been found that the system output is not only depending on the present state of the memory unit, but also depends on the present input combination, resulting in a class A type machines. Class A type machines are also called Mealy type machines, where the output to the external world depends both on present state of the memory and the present input.