2878 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 9, SEPTEMBER 2015 SiO 2 Free HfO 2 Gate Dielectrics by Physical Vapor Deposition Paul C. Jamison, Takaaki Tsunoda, Tuan Anh Vo, Juntao Li, Hemanth Jagannathan, Sanjay R. Shinde, Vamsi K. Paruchuri, and Daniel Gall Abstract— HfO 2 layers, 25-Å thick, were grown by cyclic Hf sputter deposition and room temperature oxidation steps on chemically oxidized Si(001). Subsequent in situ annealing and TiN deposition yield a high-κ gate-stack for which the original 8-Å-thick SiO 2 layer is eliminated, as confirmed by transmission electron microscopy. Transistors fabricated with this gate-stack achieve an equivalent oxide thickness in inversion T inv = 9.7 Å, with a gate leakage J g = 0.8 A/cm 2 . Devices fabricated without in situ annealing of the HfO 2 layer yield a T inv which increases from 10.8 to 11.2 Å as the oxidation time during each HfO 2 growth cycle increases from 10 to 120 s, also causing a decrease in J g from 0.95 to 0.60 A/cm 2 , and an increase in the transistor threshold voltage from 272 to 294 mV. The annealing step reduces T inv by 1.5 Å (10%) but also increases the gate leakage by 0.1 A/cm 2 (30%), and causes a 61 mV reduction in V t . These effects are primarily attributed to the oxygen-deficiency of the as-deposited HfO 2 , which facilitates both the reduction of an interfacial SiO 2 layer and a partial phase transition to a high-κ cubic or tetragonal HfO 2 phase. Index Terms— HfO 2 , high- k dielectrics, interface scavenging, MOSFET, physical vapor deposition (PVD), SiO 2 interlayer. I. I NTRODUCTION T HE leakage current across a SiO 2 gate dielectric increases by approximately one order of magnitude for every 2 Å of thickness reduction [1]. In order to enable further device scaling, HfO 2 has replaced SiO 2 as the gate dielectric in some advanced CMOS transistors, due to its higher dielectric con- stant (κ HfO 2 = 18–20 versus κ SiO 2 = 3.9) and thermodynamic compatibility with silicon. However, various researchers report the spontaneous formation of an interfacial SiO 2 or HfSiO x layer that develops between the Si substrate and the deposited Manuscript received April 30, 2015; revised June 18, 2015; accepted July 8, 2015. Date of publication August 11, 2015; date of current version August 19, 2015. This work was supported by the Division of Materials Research through the U.S. National Science Foundation under Grant 1309490. The review of this paper was arranged by Editor J. Huang. P. C. Jamison is with IBM Research at Albany Nanotech, Albany, NY 12203 USA, and also with the Department of Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180 USA (e-mail: pjamison@us.ibm.com). T. Tsunoda is with Canon Anelva Corporation, Kanagawa 215-8550, Japan (e-mail: tsunoda.takaaki@canonanelva.co.jp). T. A. Vo is with the SUNY Polytechnic Institute, Albany, NY 12203 USA (e-mail: tvo@sunycnse.com). J. Li, H. Jagannathan, and V. K. Paruchuri are with IBM Research at Albany Nanotech, Albany, NY 12203 USA (e-mail: juntaoli@us.ibm.com; jhemanth@us.ibm.com; paruchur@us.ibm.com). S. R. Shinde is with the Industrial Products Division, Canon USA, Inc., San Jose, CA 95134 USA (e-mail: sshinde@cusa.canon.com). D. Gall is with the Department of Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180 USA (e-mail: galld@rpi.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2015.2454953 HfO 2 film [2]–[6]. The most common approach to suppress the spontaneous growth of an interfacial oxide is to deliberately grow an interfacial SiO 2 layer prior to the HfO 2 deposition. This yields better control of the properties of the interfacial layer and provides a more stable surface for nucleation of the HfO 2 [7], [8]. However, it reduces the overall dielectric constant of the combined stack as, for example, replacing 25% (5 Å) of a 20-Å-thick HfO 2 film with SiO 2 reduces the effective κ of the gate dielectric by ∼50%. Atomic layer deposition is the predominant technique used to deposit HfO 2 , because it provides conformal coverage of 3-D structures [9], [10] and yields consistent performance in manufacturing environments [11]. Alternatively, physical vapor deposition (PVD) of the HfO 2 layers has also been reported, including reactive sputtering of Hf in an oxygen ambient [12], [13] and sputtering of metallic Hf followed by a high-temperature oxidation step [7], [14]. Both approaches result in the formation of an interfacial SiO 2 layer with a thickness of at least 1.5 nm. Tan et al. [7] also show that radio frequency magnetron sputter deposition of an unoxidized Hf metal layer by itself does not result in the formation of an interfacial layer on a native oxide/Si substrate and that the native oxide may be removed during such a deposition. This possible removal of the interfacial SiO 2 motivates the study presented here. In this paper, we describe a process for depositing HfO 2 by PVD that results in thinning of the SiO 2 interfacial layer and, combined with post deposition annealing, eliminates a SiO 2 layer, which is intentionally grown prior to the HfO 2 deposition. This process enables the production of transistors with a low gate leakage current density J g of 0.6 A/cm 2 at an equivalent oxide thickness in inversion T inv < 11.5 Å. By adjusting the oxidation conditions of the HfO 2 layer, during deposition and in the subsequent anneal, further T inv scaling down to 9.5 Å is demonstrated with a less than twofold increase in J g . For this paper, 10 μm 2 n-channel MOSFETs (nMOSFETs) were fabricated with a HfO 2 gate dielectric that was grown using cyclic Hf deposition and room temperature oxidation steps with various oxidation conditions. In order to demonstrate the minimization or absence of the interfacial SiO 2 layer, we present transmission electron micro- scope (TEM) micrographs of the gate region of fully processed transistors at various oxidation conditions, as well as the T inv , J g , and V t data extracted from the transistors. II. EXPERIMENTAL PROCEDURE All samples were prepared in a 300-mm semiconduc- tor development facility. The gate-stack consists of a room 0018-9383 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. 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