164 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 1, JANUARY 2000 less than the number required by other methods. After the model (1) is obtained, no more circuit simulation is needed. The number of the cir- cuit simulation required by some other global approximation methods, such as group method of data handling (GMDH) and maximally flat quadratic interpolation (MFQI) [8], is not very large, but their accuracy is difficult to guarantee. This novel algorithm can get a high accuracy with a reasonable cost. Generally speaking, the gradient-dependent algorithm has a high convergence speed, but they can find only a local optimum point. If the Taguchi algorithm is utilized, then at least circuit simulations are needed for each iteration. If ten iterations are necessary to find the optimum point, then more than sim- ulations are needed. It is still a large number, and the optimum is only local. Hence, it is clear that the method presented in this paper is much better as the complexity of the algorithm is only linear and the function approximation is virtually global as confirmed by a large checking set. V. CONCLUSION A two-step algorithm to search for the global optimum design and re- duce performance spread efficiently has been presented. The total cost has algorithm complexity which is much lower than that of the gradient-dependent algorithm and some other algo- rithms. LHD provides enough information from the smallest number of circuit simulations to arrive at the global approximation. Meanwhile, this novel global approximation utilizes the information about the cir- cuit itself efficiently, and so the cost for calculation is very low. Then, GA is utilized to find the global optimum point. The global optimum solution not only meets performance criteria but also reduces the spread in the performance functions to yield a much value-added design. From the examples, it is obvious that this novel methodology is likely to at- tain a global optimum result with a very low cost. REFERENCES [1] R. Spence and R. S. Soin, Tolerance Design of Electronic Cir- cuits. Workingham, U.K.: Addison Wesley, 1988. [2] D. E. Hocevar, P. F. Cox, and P. Yang, “Parametric yield optimization for MOS circuit blocks,” IEEE Trans. Computer-Aided Design, vol. 7, June 1988. [3] M. Singha and R. Spence, “The parametric yield enhancement of inte- grated circuits,” Int. J. Circuit Theory Applicat., vol. 19, pp. 565–578, 1991. [4] M. Conti, S. Orcioni, and C. Turchetii, “Parametric yield optimization of MOS VLSI circuits based on simulated annealing and its parallel imple- mentation,” IEE Proc.Circuits Devices Syst., vol. 141, no. 5, Oct. 1994. [5] M. D. McKay, R. J. Beckman, and W. J. Conover, “A combination of three methods for selecting values of input variables in the analysis of output from a computer code,” Technomet., vol. 21, no. 2, May 1979. [6] M. Keramat and R. Kielbasa, “Modified Latin Hypercube Sampling Monte Carlo (MLHSMC) estimation for average quality index,” Analog Integr. Circuits Signal Processing, vol. 19, no. 1, pp. 87–98, Apr. 1999. [7] J. Chen and M. A. Styblinski, “A systematic approach of statistical mod- eling and its application to CMOS circuits,” in Proc. IEEE Int. Symp. Circuits and Systems’93, Chicago, IL, May 1993, pp. 1805–1808. [8] M. A. Styblinski and S. Aftab, “Combination of interpolation and self-organizing approximation techniques—A new approach to circuit performance modeling,” IEEE Trans. Computer-Aided Design, vol. 12, Nov. 1993. [9] J. C. Zhang and M. A. Styblinski, Yield and Variability Optimization of Integrated Circuits. Boston, MA: Kluwer Academic, 1995. [10] N. K. Raghu, “Off-line quality control, parameter design, and the Taguchi method,” J. Quality Technol., vol. 17, no. 4, Oct. 1985. [11] Z. Michalewicz, Genetic Algorithms Data Structures Evolution Programs. New York: Springer-Verlag, 1992. [12] Y. Shen and R. M. M. Chen, “Application of genetic algorithm for re- sponse surface modeling in optimal statistical design,” in , 11995 IEEE Int. Symp. Circuits and Systems, vol. 3, 1995, pp. 2152–2155. [13] N. J. Elias, “Acceptance sampling: An efficient, accurate method for es- timating and optimizing parametric yield,” IEEE J. Solid-State Circuits, vol. 29, Mar. 1994. [14] S. W. Pan and Y. H. Hu, “PYFS—A statistical optimization method for integrated circuit yield enhancement,” IEEE Trans. Computer-Aided Design, vol. 12, Feb. 1993. [15] M. D. Meehan and J. Purviance, Yield and Reliability in Microwave Cir- cuit and System Design. Boston, MA: Artech House, 1993. [16] M. C. Bernardo, R. Buck, and L. Liu, “Integrated Circuit Design Op- timization Using a Sequential Strategy,” IEEE Trans. Computer-Aided Design, vol. 11, Mar. 1992. [17] R. X. Gu, K. M. Sharaf, and M. I. Elmasry, High-Performance Digital VLSI Circuit Design. Boston, MA: Kluwer Academic, 1996. [18] L. Ingber and B. E. Rosen, “Genetic algorithms and very fast simulated reannealing,” Math. Comput. Model., vol. 16, no. 11, pp. 87–100, 1992. Estimation of Signal Transition Activity in FIR Filters Implemented by a MAC Architecture S. Nikolaidis, E. Karaolis, and E. D. Kyriakis-Bitzaros Abstract—A novel method for the accurate calculation of the transition activity at the nodes of a multiplier-accumulator (MAC) architecture im- plementing finite impulse response filters is proposed in this paper. The method is developed for input signals, which can be described by a sta- tionary Gaussian process. The transition activity per bit of a signal word is modeled according to the dual-bit-type (DBT) model and it is described as a function of the signal statistics. An efficient analytical method has been developed for the determination of the signal statistics at each node of the MAC architecture. It is based on the mathematical formulation of the mul- tiplexing in time of signal sequences with known statistics. The effect of the multiplexing mechanism on the breakpoints of the DBT model, which in- fluences significantly the accuracy of the method, is also determined. Sev- eral experiments both with synthetic and real data have been conducted. The numerical results produced by the proposed models are in very good agreement with the measured values of the transition activity. Index Terms—DSP synthesis, low-power design, power modeling and es- timation, VLSI. I. INTRODUCTION Power dissipation has become a major concern in very large scale integration (VLSI) design during the last years [1]–[3]. The dominant factor of power dissipation in CMOS circuits is the dynamic power con- sumed during charging/discharging the load and parasitic capacitances, while static and short circuit power dissipation have little contribution to the total power budget in a well designed circuit [1]. Since dynamic power dissipation depends on the number of transitions occurring at the capacitive nodes, estimation of the average number of bit-level signal Manuscript received October 15, 1998; revised September 16, 1999. This paper was recommended by Associate Editor M. Pedram. S. Nikolaidis and E. Karaolis are with the Section of Electronics and Computers, Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki, Greece. E. D. Kyriakis-Bitzaros is with the Institute of Microelectronics, NCSR “Demokritos,” Agia Paraskevi 15310, Greece. Publisher Item Identifier S 0278-0070(00)01373-7. 0278–0070/00$10.00 © 2000 IEEE