GaAs BiFET Process and High-Speed Circuits** P.J. Zampardi, S.M. Beccue, K. Pedrotti, J. Yu, W. J. Ho, R.L. Pierson, M.F. Chang, K.C. Wang Rockwell International Science Center, Thousand Oaks, CA 91360 (presented at International Semiconductor Device Research Symposium, Virginia, Dee 2. 1993) ABSTRACT In this work, we describe some of the first circuits demonstrated using monolithically integrated GaAlAs/GaAs Heterojunction Bipolar Transistors (HBTs) and Metal-Semiconductor Field Effect Transistors (MESFETs). The dcvcloped fabrication technology has several advantages over other integration approaches. Several circuits fabricated using this technology arc also discussed, they include a memory bit cell, a laser driver, and an optoelectronic receiver. INTRODUCTION The integration of Metal-Semiconductor Field Effect Transistors (MESFETs) with Hetcrojunction Bipolar Transistors (HBTs) has significant impact on the design of high performance gallium arsenide circuits and systems. The combination of the HBT’s high switching speed, high drive capability, and low l/f noise and the FET’s low noise, high input impedance, high density and yield, offer designers a great deal of flexibility and novel circuit opportunities. In particular, the addition of MESFETs to an HBT process (forming a Bipolar- FET or BiFET process) will provide high input impedance for sample-and-hold post-amplifiers, active loads and low voltage currents sinks for minimizing power consumption, and floating current sources to provide high gain. This combination can provide higher functionality per chip (functional density) and offer new circuit opportunities such as a DRFM on a chip, and low power high-speed SRAMs using HBT driving circuitry and FET memory cells. A/D and D/A convcrtcrs will also benefit from this emerging technology. In addition to the new circuit opportunities this technology allows, there are several distinct advantages it holds over other integration techniques for HBTs and FETs. The most obvious advantage of this approach is the use of the already existing emitter epilayers to define the active channel for the FETs. This provides a more planar structure than if we had defined the FET from collector layers [ 11, eliminates the need for material regrowth (since the entire structure is grown in a single epitaxial sequence), and avoids the need for selective implantation to form the p+ layers [2]. Excellent device characteristics have been obtained using this process; transconductancc of 200-450 mS/mm and low output conductance (<lmS/mm) have been observed from FETs made in this process. A unique feature of this process is that the backgate contacts to the buried p+ layer allow electrical modulation of the backgate and provides enhanced resistance to substrate rclatcd side-gating and radiation effects. This process is quasi-planar and highly synergistic with already existing HBT fabrication processes. The only disadvantage we have observed is that the p+ layer increases the drain-base capacitance which slightly degrades the FET high-speed performance [ 31. We will begin by discussing this process as it pertains for the fabrication of high-speed integrated circuits. The characteristics of devices made from this process will be discussed along with the fabrication of the circuits. WC will then discuss some examples of circuits that have been demonstrated in our laboratory using this process. CIRCUIT FABRICATION Rockwell’s Digital HBT fabrication process is well established [4]. The layer structure used in this process is a standard emitter-up, single heterojunction HBT structure that was produced by MOCVD on a semi-insulating GaAs **This work was partially supported by Air Force Wright Patterson Laboratory under contract #F336 15 90-C-I 50.5.