Accurate Prediction of Resistor Variation Using Minimum Sized Five-Resistor TLM Dheeraj K. Mohata 1 , Crystal Chueng 1 , Brian G. Moser 1 , and Peter J. Zampardi 2 1 Qorvo Inc., 7628 Thorndike Road, Greensboro, NC 27409, USA 2 Qorvo Inc., 950 Lawrence Drive, Newbury Park, CA 91320, USA e-mail: Dheeraj.mohata@qorvo.com Phone: +1-336-678-7161 Keywords: Thin film resistor, TLM, ｨW, variation analysis, propagation of errors method Abstract In this work we show the importance of considering di- mensional variation (ｨL and ｨW) to accurately predict re- sistor variation for circuit design. To aid with our predic- tion, we first discuss the importance of measuring all physical components of a resistor (RSH, ｨL, and ｨW) using the novel 5-R TLM technique and discuss advantages over conventional techniques. Then, we introduce and apply the propagation of errors statistical technique to formu- late a method for accurately predicting resistor variation using nominal values and standard deviations of its com- ponents. Finally, we show how designers can exploit this statistical technique in predicting resistor variations in ad- vance to save time and resources for a robust, high yield circuit design. INTRODUCTION On-chip resistors are very useful in MMIC circuit design. They are used for current regulation, voltage division, imped- ance matching, gain and thermo-electric stabilization, and other requirements that ensure proper functioning of any cir- cuit. Unfortunately, like other devices, on-chip resistors suf- fer manufacturing process variation and are never ideal. While resistive film thickness variation drives sheet resistance (R SH) variation, photolithography and etch process variations result in size variation which can significantly impact resis- tors drawn at or near the minimum size allowed. With the state of the art growth and deposition techniques, compound semiconductor foundries have obtained reasonably good con- trol over the resistive film thickness but variations due to di- mensions and their impact have either been ignored or the im- pact on circuit performance has not been well understood. In this work, we first discuss the importance of extracting dimensional variation, especially of the width (ｨW). Sec- ondly, we introduce a novel five-resistor transfer-length method (5-R TLM) and discuss the advantages in measuring all relevant resistor parameters over conventional methods. Finally, we discuss how to exploit propagation of errors [1] statistical analysis to more accurately predict variations for any given resistor type. Fig. 1 shows a typical schematic of a rectangular resistor. L D and WD are drawn length and width of the resistor, while LA and WA are actual (electrical) dimensions as measured and extracted by various DC process control monitor (PCM) tests. ｨL=LA-LD and ｨW=WA-WD are the differences in the drawn vs. electrical dimensions. From drift theory and Ohms law, we know that any Ohmic resistor can be expressed as: ൌ ௌு ܮ ஽ ൅ ｨ ܮ  ஽ ൅ ｨ ൅ ʹ ஼ െ െ െ െ െ െ െ െ െ െ െ െሺͳሻ Where, RC is the contact resistance of the resistor terminals. Figure 1- Typical definition of a resistor. When drawing resistors, designers use standard resistors available in the process design kit (PDK) to make sure tech- nology-relevant resistor and contact layers are used and that their designs adhere to the layer design rule. Most PDKs de- fine library resistors with R SH and RC and may contain infor- mation about their standard deviations (ʍ), but lack infor- mation about ｨL, ｨW and their ʍs. While ｨL can be approx- imated using RC as ο ܮൌ ʹ ஼ ൈ Ȁ ௌு ǡ ｨW needs a sepa- rate extraction. When circuit size is not a constraint, it is wise to draw resistors wide such that WD>>ｨW. However, when the footprint is tight, it becomes necessary to draw resistors narrow and close to Wmin. Thus, it becomes necessary to con- sider the impact of ｨW on resistor variation. To properly predict dimensional variation, we must have (a) accurately measured dimensional variation from utilizing an appropriate PCM structure and (b) a handy method for the L D W D L cont W A L A 5a 65 CS ManTech Conference, May 16th - 19th, 2016, Miami, Florida, USA