T ECHNICAL F EATURE implementation of statistical simulations in microwave designs (and III-V designs, specifi- cally) is very limited, even though it is well es- tablished in the silicon (Si) digital or analog- mixed signal worlds. What are the barriers? The methodology used in the Si design com- munity is usually built around Monte Carlo (MC) simulations. 1-4 MC-based simulation is inherently time consuming, but necessary for most Si designs, where neighboring device mismatches are critical due to much smaller device sizes. The complicity and huge amount of time makes it “unfit” to III-V designs, where wafer turn-around time is much shorter (weeks rather than months, typical for Si de- signs). Si foundries may also provide “corner” 136 MICROWAVE JOURNAL ■ SEPTEMBER 2008 Y. YANG, P. ZAMPARDI, M. FREDRIKSSON, J. XU, S. CHEN AND G. ZHANG Skyworks Solutions Inc. Newbury Park, CA J. SIFRI Agilent Technologies/Agilent EEsof EDA Westlake Village, CA I n wireless handset design, specifically power amplifiers (PA), there is constant pressure to improve time-to-market while maintaining high yields. To meet these de- mands, designers need to evaluate current de- sign practices and identify areas for improve- ment. Presently, most PA designers spend a great deal of time bench-tuning to optimize circuits. Since this is very time consuming, the main consideration is obtaining the best “nominal” performance, and process variation (or whether the wafer used for tuning is opti- mal) is generally an afterthought. One common occurrence is that new cir- cuit topologies are tried and minimal sample sizes are taken on a single wafer, often leading to “measured hero results.” However, once the design is run over many wafers, normal process variations may result in large perfor- mance changes that may give unacceptable yield levels. These variations are often blamed on the starting material or the fabrication process but, in reality, are usually due to ex- pected process variations. Including process statistics in the simula- tion phase would greatly reduce the occur- rence of these frustrating events. However, AN INNOVATIVE AND INTEGRATED APPROACH TO III-V CIRCUIT DESIGN 9M30 FINAL 8/27/08 2:02 PM Page 136