JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 19, NO. 1, FEBRUARY 2010 55 A Novel Micromachining Process Using DRIE, Thermal Oxidation, Electroplating, and Planarization to Create High Aspect Ratio Coplanar Waveguides Shane T. Todd, Member, IEEE, Xiaojun T. Huang, John E. Bowers, Fellow, IEEE, and Noel C. MacDonald, Fellow, IEEE Abstract—A micromachining process has been developed to cre- ate high aspect ratio coplanar waveguides (HARCs). The process creates tall Si mesas using deep reactive-ion etching and converts them into solid SiO 2 mesas using thermal oxidation. Tall Au con- ductors are deposited using electroplating and planarized using lapping and chemical-mechanical planarization. The solid SiO 2 mesas form the dielectric gap between the tall Au conductors, resulting in HARCs with a planar surface. The tall conductor side- walls created from the high aspect ratio process reduce the trans- mission line resistance, which allows the lines to have lower loss at low impedances compared to conventional transmission lines. Transmission lines with characteristic impedances of 16–21 Ω have been fabricated on high-resistivity Si. Transmission line characteristics were measured from 1 to 50 GHz and showed an attenuation of 1.0–1.4 dB/cm at 10 GHz. Measurements were compared to HFSS simulations and showed reasonable agreement over the frequency range. [2009-0132] Index Terms—Coplanar waveguides (CPWs), electroplating, high aspect ratio, RF MEMS, thermal oxidation, transmission lines. I. I NTRODUCTION C ONVENTIONAL transmission lines, such as microstrip and coplanar waveguides (CPWs), can suffer from high dielectric loss when fabricated on a substrate with a substantial loss tangent. Microstrip is particularly vulnerable to dielectric loss because most of the electric field is concentrated within the substrate. CPW is also vulnerable to dielectric loss because fringing fields at the edge of the conductors penetrate the substrate. CPW can also suffer from high conductor loss due to high current density caused by its thin conductors. Micro- machining methods can be used to fabricate transmission lines with reduced dielectric and conductor loss. Micromachined transmission lines can also offer other advantages, includ- ing improved isolation, higher packing density, and improved Manuscript received May 16, 2009; revised October 21, 2009. First pub- lished December 15, 2009; current version published February 3, 2010. This work was supported by The Kavli Foundation. Subject Editor O. Tabata. S. T. Todd and J. E. Bowers are with the Department of Electrical and Com- puter Engineering, University of California, Santa Barbara, CA 93106 USA (e-mail: stodd@ece.ucsb.edu; bowers@ece.ucsb.edu). X. T. Huang and N. C. MacDonald are with the Department of Mechanical Engineering, University of California, Santa Barbara, CA 93106 USA (e-mail: huang@engineering.ucsb.edu; nmacd@engineering.ucsb.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JMEMS.2009.2036745 power handling. Table I summarizes previously reported mi- cromachined transmission lines. Micromachining methods can lower dielectric loss in trans- mission lines on lossy substrates (particularly silicon) by re- ducing the electric field exposure to the substrate. A popular approach to isolate electric fields from the substrate is to create a distance between the transmission lines and the sub- strate through substrate removal or transmission line elevation. Chi and Rebeiz [1] demonstrated a micromachining method for fabricating microstrip and CPW on Si. The fabrication utilized a backside silicon wet etch that removed Si underneath the transmission lines, allowing for minimal interaction of the electric field with the substrate. A similar method was used by Herrick et al. [2] to achieve grounded CPW on silicon. Tea et al. [3] utilized XeF 2 undercut etching to remove Si un- derneath CPW in a post-CMOS process. Ponchak et al. [4] de- veloped a micromachining method where CPW was patterned on thick polyimide on Si. The thick polyimide elevated the CPW so that most of the electric field did not penetrate the Si substrate. Another approach to reduce dielectric loss is to shield the fields from the substrate using a ground plane. Jeong et al. developed a multilayer process where transmission lines were micromachined on a ground plane that shielded fields from the Si substrate. Low-loss coaxial, stripline, microstrip, and CPW transmission lines were fabricated on Si using this method [5]. Other micromachining methods have used the ground-plane- shielding approach to fabricate microstrip [6]–[9], coaxial [8], [10]–[12], semicoaxial [8], [13], and CPW [8] transmission lines. Micromachining can also reduce conductor loss by increas- ing the transmission line surface area. This is mainly accom- plished by creating conductors with tall sidewalls that allow the current to spread over a larger area, thus reducing the transmis- sion line resistance. Micromachined coaxial transmission lines are an excellent demonstration of reduced conductor loss. Low- loss coaxial transmission lines are difficult to fabricate using standard microfabrication technology because small gaps and conductor dimensions are necessary to make lines with stan- dard impedances. The small dimensions result in high current densities and high loss [14]. Micromachining techniques have been developed to increase the coaxial dimensions, making lines with loss that is compara- ble to microstrip. Brown et al. [10] demonstrated a multilayer 1057-7157/$26.00 © 2009 IEEE Authorized licensed use limited to: Univ of Calif Santa Barbara. Downloaded on February 2, 2010 at 21:09 from IEEE Xplore. Restrictions apply.