Demonstration of contention resolution between two 40 Gb/s packet streams using multiple photonic chip optical buffers Emily F. Burmeister, John P. Mack, Henrik N. Poulsen, Biljana Stamenić, Milan Mašanović, Daniel J. Blumenthal, John E. Bowers ECE Department, University of California, Santa Barbara, California, USA 93106-9560 e-mail: {emily, jmack, henrik, biljana, mashan, danb, bowers}@ece.ucsb.edu Abstract Integrated optical RAM using InP switches with silica waveguide delays perform contention resolution with 99% packet recovery for 40-byte packets. Two buffered inputs and two packet depths are demonstrated. Introduction Optical router technology has the potential to address the power and footprint limitations of increasingly higher capacity electronic routers. However, a practical integrated optical buffer that can operate with the required signal fidelity and control interface is necessary to handle contention. To date, optical buffering has been reported using discrete technologies, which greatly limits the buffer performance, cost, and eventual depth. In this paper we report the first buffering demonstration of IP- sized packets by chip-scale optical memory for multiple input ports under scheduling control. The buffers ran autonomously using a payload envelope detect circuit to discern upcoming contention, an arbiter to make buffering decisions, and electronic channel processors to send signals to the buffer device. The optical RAM (random access memory) approach presented here is advantageous because it can store 40 Gb/s, 40-byte packets in a small footprint [1]. Delay line buffers have been reported with excellent performance [2], but chip-level integration and system demonstrations are necessary for optical buffering to become a reality. Buffer design Recirculating buffers have the advantage of requiring only one major component while providing dynamic control of storage times with the granularity of the delay line length. The buffers used in this work combine 2x2 InP-based switches with on-chip silica-on-silicon delay lines that are 2.65 m in length i.e. 12.8 ns delay (Fig. 1). The delay line length is chosen to be slightly longer than the length of a 40 Gb/s, 40-byte packet and its guard bands; thus allowing the greatest resolution in possible delay times. The InP 2x2 switch meets the performance requirements to realize a recirculating packet buffer compatible at the system level. Our buffer design operates at 40 Gb/s, has high extinction ratios (>40 dB) for cascadability [3] and can switch in under 2 ns, which is within packet guard bands. The semiconductor optical amplifier (SOA) gate matrix switch is the best switch choice for recirculating buffers primarily because it provides high extinction while meeting the speed needs and compensates for splitter and delay line loss. Switching between ports is controlled by turning on and off the switching amplifiers placed at the center of the chip (Fig. 1a). The input light is split between the delay loop input and the output port and is amplified for the desired direction while the other half of the signal is absorbed by the quantum wells in the amplifier that is turned off. The fabricated switches met all of the performance requirements. Figure 1: (a) Schematic of buffer device and (b) SEM of InP 2x2 SOA gate matrix switch. Silica-on-silicon waveguides are used to provide a nearly transparent delay loop while being relatively compact. Passive measurements were taken over a wavelength range from 1525 nm to 1575 nm for the silica waveguides. Measurements show propagation losses of less than 0.04 dB/cm at 1550 nm, and varied less than 0.001 dB/cm over the 50 nm span. Polarization dependent loss for 200 cm of waveguide was approximately 1 dB and chromatic dispersion was approximately 130 ps/nm•km. The waveguide design is conservatively limited to a minimum bend radius of 6 mm, but was spiraled on the chip to reduce space. The area needed for 2 m of delay is 6.4 cm 2 . We.2.D.3 ECOC 2008, 21-25 September 2008, Brussels, Belgium Vol. 3 - 115 1 978-1-4244-2228-9/08/$25.00 (c) 2008 IEEE