International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 03 Issue: 08 | Aug-2016 www.irjet.net p-ISSN: 2395-0072 © 2016, IRJET | Impact Factor value: 4.45 | ISO 9001:2008 Certified Journal | Page 830 Design and Implementation of 128-bit SQRT-CSLA using Area-delay- power efficient CSLA Nagaraju Tatipudi 1 and TVS Divakar 2 1 M. Tech Scholar, Department of ECE, GMR Institute of Technology, Rajam, Srikakulam, Andhra Pradesh, India. 2 Sr. Assistant Professor, Department of ECE, GMR Institute of Technology, Rajam, Srikakulam, Andhra Pradesh, India. -----------------------------------------------------------------------------***------------------------------------------------------------------------------ Abstract—In VLSI, area, delay and power are the crucial parameters. To minimize them we have a lot of methods, but there is still a requirement of a robust algorithm to reduce them. By the use of efficient carry select adder, we can optimize the area, delay, power compared to the conventional adders. The conventional carry select adder (CSLA) and BEC-based CSLA adder are the references, on analysing these adders we have observed the data dependency and identified the unnecessary logic operations, on remove all the unnecessary logic operations existent in conventional CSLA, the proposed new logic formulation for conventional CSLA works effectively with less area and less delay than newly proposed BEC-based method, in consequence of small carry output delay. The proposed method is suitable for SQRT- CSLA, which gives better results than conventional SQRT-CSLA which has less area, less delay for different bit widths, on an average. Results of synthesis show that BEC- SQRT CSLA design consumes more energy and more ADP than proposed SQRT-CSLA on average, for different bit widths. Furthermore, in this paper, we have proposed 128-bit SQRT-CSLA with proposed CSLA. Index Terms—VLSI, CSLA, Area-delay-power efficient design, SQRT-CSLA, Xilinx. I. INTRODUCTION Adder is a digital circuit that works on binary bits for addition operation. Generally, the adder is used in the arithmetic logic unit, which plays a key role. It is also used in some other parts of the processor for calculating the address, table indices, increment and decrement operators, and similar operations. These are the references, for increasing significant priority of adders in electronics. Several adders are used in complex digital signal processing (DSP) system. An efficient adder can give the high performance, area efficient, low power, for the complex DSP systems. High performance, low power, area efficient VLSI designs are utilized as a part in mobile devices, Multistandard remote beneficiaries and biomedical instrumentation [1] [2] progressively used, for these three parameters mainly depends on efficient adder. Ripple carry adder (RCA) is a simple design adder, in RCA carry propagation is the main concern. To minimize the carry propagation delay (CPD), carry look-ahead adder and carry select adders are have been recommended. The conventional CSLA has RCA-1 unit, RCA-2 unit and selection unit, the RCA-1 and RCA-2 units are generates pair of sum words and output carry bits accordingly to their relative anticipated input carry (Cin = 0 & 1), then selection unit select the one out of the sum word and one out of the output carry bits, these are the final sum and final output carry [3] respectively. The CSLA gives better performance in terms of CPD but the design is bit complicated, due to the dual use of RCAs. Few attempts have been made to ignore the use of RCA as twice. Instead of has two RCAs. Kim and Kim [4] have implemented with one RCA circuit and one add-one circuit which is operated with mux. Ramkumar and kittur [6] were suggested BEC-based CSLA. The BEC-based CSLA full fill the less logic resources requirement but it has marginally high delay. The CBL- based CSLA [7], [8] was suggested by I.-C. Wey, S. Manju. The CBL-based CSLA greatly less logic resources [7] but it has high CPD, which is mostly similar to RCA. To eliminate this problem, The SQRT-CBL was suggested by [8]. In[5]it is defined SQRT-CSLA, for the purpose of large bit widths using with less area but the cascading structure of connecting CSLAs is the main concern to increase the size.