International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 03 Issue: 08 | Aug-2016 www.irjet.net p-ISSN: 2395-0072 © 2016, IRJET | Impact Factor value: 4.45 | ISO 9001:2008 Certified Journal | Page 1536 High Speed ALU Processor by Using Efficient Multiplication Technique RAHUL SHARMA 1 , DEEPAK KUMAR 2 M. Tech. Scholar 1 , Asst. Professor 2 Department of Electronics and communication Vidhyapeeth Institute of Science and Technology Bhopal, MP, India ---------------------------------------------------------------------***--------------------------------------------------------------------- Abstract - As the scale of integration keeps growing, more and more sophisticated and fast processing systems are being implemented on a VLSI chip. These fast processing system applications not only demand great computation capacity but also consume considerable amount of power. And the ALU are main functional unit in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. So the performance such VLSI circuit is dependent on the performance of the ALU. The performance of ALU is mainly depends on the performance of multiplier because the multiplier is generally the slowest and area consuming element in the system. Hence, optimizing the speed and area of the multiplier is a major design issue. Here, a High-speed multiplier is designed and analyzed which is based on the algorithm named as DzUrdhva Tiryakbhyamdz sutra ȋUT TechniqueȌ. Traditionally, this well known Technique has been used for fast multiplication. The proposed algorithm is developed using VHDL. Implementation has been done using Xilinx14.2, Spartan 6. Key Words: ALU, Multiplier, Adder, Logical Unit, Multiplexer, Vedic mathematics. 1. INTRODUCTION An arithmetic logic unit (ALU) is a Computation unit that performs various arithmetic (addition, subtraction, multiplication) and logical operations (AND, OR, INVERTER). And thatǯs why the ALU is called heart of microprocessor, microcontroller and digital signal processor. The performance of Fast processing system is dependent on the speed of the ALU. The speed of ALU depends greatly on the multiplier. In algorithmic and structural levels, numerous multiplication techniques have been developed to enhance the efficiency of the multiplier which concentrates in reducing the partial products and the methods of their addition but the principle behind multiplication remains the same in all cases. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. Employing these techniques in the computation algorithms of the coprocessor will reduce the complexity, execution time, area, power etc. Though there are many sutras employed to handle different sets of numeric, exploring each one gives new results. Our work has proved the efficiency of Urdhva Tiryakbhyam– Vedic method for multiplication. The organization of paper starts with a brief introduction that describes in the section I. Thereafter, Section II describes the Multiplication technique. Section III describes the Architecture of proposed multiplier. Section IV describes the design and implementation of ALU based on UT Technique module in XilinxISE14.2. Section V comprises of Result and Discussion in which computational path delay obtained. Finally Section VI comprises of Conclusion. 2. MULTIPLICATION TECHNIQUE Urdhva Tiryakbhyam (UT) technique is sutra of Vedic mathematics used for multiply two given numbers in Decimal number system. However, we put forward the multiplication of two binary numbers using this technique. The literal meaning of UT is DzVertically and crosswisedz and the multiplication happens in this fashion. UT is a novel concept through which introduces a parallel execution of partial products and sums which is explained in fig- 1. The word Vedic is derived from the word ǮVedaǯ which means the store-house of all knowledge. Hundred years ago(in between 1911 and1918) Sanskrit scholars Jagadguru Swami Sri Bharati Krishna Tirthaji translated the Vedic documents and got surprised about the depth of knowledge enriched in that and became very popular to achieve high speed processing of the data. Vedic mathematics mainly based on 16 Sutras dealing with various branches of mathematics like arithmeticǯs, algebra, geometry etc. these sutras with their brief meaning are given bellow. 1) (Anurupye) Shunyamanyat -If one is in ratio, the other is zero. 2) ChalanaKalanabyham -Differences and similarities. 3) Ekadhikina Purvena- By one more than the previous One. 4) Ekanyunena Purvena -By one less than the previous one. 5) Gunakasamuchyah-Factors of the sum is equal to the sum of factors. 6) Gunitasamuchyah-The product of sum is equal to sum of the product. 7) Nikhilam Navatashcaramam Dashatah -All from 9 and last from 10.