International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 03 Issue: 08 | Aug -2016 www.irjet.net p-ISSN: 2395-0072 © 2016, IRJET | Impact Factor value: 4.45 | ISO 9001:2008 Certified Journal | Page 1873 Implementation of Sequential Circuit using Reversible Fredkin gate on FPGA Vandana Singh 1 and Abhishek Sharma 2 Department of Electronics and Communication Engineering , RGPV Bhopal Sagar Institute of Research and Technology , RGPV University Bhopal, India. 1 singh.vandana2411@gmail.com, 2 abhishektit09@gmail.com Abstract: In this paper we propose the design of testable sequential circuit by two vector using conservative logic. The proposed sequential circuits based on conservative logic outclass the traditional sequential circuits built using classical gates in terms of testability. Any sequential circuits based on conservative logic can test for stuck-at 0 and stuck-at 1 fault by using two vectors 0 and 1. The design of testable Master slave D flip-flop, Double Edge triggered flip flop (DET) flip-flop using two vectors 0 and 1 are presented. The importance of the proposed work is that we are designing reversible sequential circuits suitable for testing. Hence both conservative logic and reversible logic is used. In the proposed work, we design a reversible sequential circuit using Fredkin gate. Fredkin gate is the only reversible gate which supports both conservative and reversible logic and also having less quantum delay. Index terms: Fredkin gate, D flip flop, reversible logic, conservative logic. I. INTRODUCTION Conservative logic is a logic family that displays the property that there are equal numbers of ͳǯs in the output as therein the input. Conservative logic can be reversible or may not be reversible in nature. By using conservative logic it has zero internal power dissipation which is an added advantage to this proposed technique. Reversibility is the property which shows one-to-one mapping between input and output vector; thus the vector of input states can be always reconstructed from the vector of output states. Reversible logic does not allow fan- out to occur, it means for each input corresponding output is produced. Hence for 1 input multiple outputs are not possible; this is strictly restricted by reversible logic which results testing to be easy. Conservative logic is also called reversible conservative logic when there is one-to-one mapping between input and output vectors along with the property that there are equal numbers of ͳǯs in the outputs as in the inputs. If a circuit is designed in an irreversible manner then there will be a bit of information lost and which results in heat dissipation. The line of approach offered by conservative logic avoids a number of dead ends that are found in traditional models and opens up fresh views. According to landauer principle one bit of information lost is equal KTln2 joules of energy lost, where K is the Boltzmann constant and T is the temperature in which operation is performed. So to reduce this energy lost completely we use reversible logic. And also reversible logic completely reduces heat dissipation. Reversible logic has received great attention in the recent years due to their ability to reduce the power dissipation which is the main requirement in low power VLSI design. Reversible logic takes care of Fan-out problem. It supports the process of running the system both forward and backward. The proposed technique will take care of the fan-out (FO) at the output of the reversible latches and can also disrupt the feedback to make them suitable for testing by only two test vectors, all 0s and all 1s. By this way we can easily test the circuit with ease. In other words when circuit is executed in normal mode, feedback will be present because to compensate for the extra inputs. And similarly when executed in test mode its feedback is disrupted and the circuit is tested for stuck-at faults. So proposed technique is divided in to two modes normal and test mode. Fan-out leads to increased capacitive load on the driving gate, and therefore longer delay. So the fan-out problem is