International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 03 Issue: 05 | May-2016 www.irjet.net p-ISSN: 2395-0072 © 2016, IRJET | Impact Factor value: 4.45 | ISO 9001:2008 Certified Journal | Page 578 Front end Design of shift registers using latches Nikitha.N(VLSI design and embedded system (M-tech),BITM,Bellary) Pramod Mutalik (Assistant professor, BITM BELLARY), Department of Electronics and Communication Engineering ------------------------------------------------------------------------------------------------------------------ Abstract: This paper proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip- flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. This Proposed System Designed using Verilog HDL and Simulated through Modelsim 6.4 c and Synthesis by Xilinx tool. I. INTRODUCTION As we know that shift register are the basic building blocks in a VLSI circuit. Which are commonly used in many applications, such as digital filters, communication receivers and image processing ICs. Nowadays, as the size of the image data has continuously increasing due to the high demand for high quality image data, the word length of the shifter register increases to process large image data in image processing ICs. Process like image-extraction and vector generation VLSI chip uses a 4K-bit shift register. Hence word length of the shifter register increases, the area and power consumption of the shift register become important design considerations. The architecture of a shift register is quite simple. An N-bit shift register is composed of series connected N data flip-flops. The speed of the flip-flop is less important than the area and power consumption because there is no circuit between flip-flips in the shift register. Recently, pulsed latches have replaced flip-flops in many applications, because a pulsed latch is much smaller than a flip-flop. But the pulsed latch cannot be used in a shift register due to the timing problem between pulsed latches. This paper proposes implementation of shift registers using pulsed latches, which makes use of a multiple non overlapping delayed pulsed clock signals instead of single pulsed clock signal. II. OBJECTIVE AND TOOLS USED Project Objective The main objective of this project is design and implementation of shift registers using pulsed latches. Simulation Software: Modelsim 6.4c is used for simulation of the proposed design. Synthesis tool 9.1: Xilinx 9.1 is used for synthesis of the design verilog code. III. IMPLEMENATION (a)