Efficient CMOL Nanoscale Hybrid Circuit Cell Assignment Using Simulated Evolution Heuristic Sadiq M. Sait Department of Computer Engineering Center for Communications and IT Research Research Institute King Fahd University of Petroleum & Minerals Dhahran-31261, Saudi Arabia. sadiq@kfupm.edu.sa Abdalrahman Arafeh Department of Computer Engineering King Fahd University of Petroleum & Minerals Dhahran-31261, Saudi Arabia. arafeh@kfupm.edu.sa ABSTRACT Recently, many CMOS/nanodevices hybrid architectures have been proposed, the new architectures combine the flex- ibility and high fabrication yield advantages of CMOS tech- nology with nanometer scale latching devices. CMOL, a novel architecture that uses two levels of perpendicular nano- wires as crossbar interconnection on top of inverter-based CMOS stack, offers significant density advantages and over- comes physical barriers of lithography-based fabrication. However, the confined connectivity of CMOL nanofabric to only cells that are located within proximity square-like con- nectivity domain, reduces the flexibility of VLSI design au- tomation and further complicates cells placement. In this paper we use Simulated Evolution algorithm to solve the NP-hard problem of assigning NOR/INV gates to CMOL array. The main objective is to reduce the total number of buffers that must be inserted between cells that require long wires to connect. A novel goodness and allo- cation functions are introduced for efficient exploration of search space. Empirical results for ISCAS’89 benchmarks are compared with previous solutions using GA, MA, and LRMA heuristics. Our approach is able to find better so- lutions for all tested benchmarks and with 82% average re- duction in CPU processing time. Categories and Subject Descriptors B.7.2 [Hardware]: Integrated Circuits—Design Aids, Place- ment and Routing ; B.7.1 [Hardware]: Integrated Circuits— Types and Design Styles, Gate Arrays General Terms Algorithms, Design Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. GLSVLSI’12, May 3–4, 2012, Salt Lake City, Utah, USA. Copyright 2012 ACM 978-1-4503-1244-8/12/05 ...$10.00. Keywords CMOL, Simulated Evolution, Combinatorial Optimization, Search Heuristics, VLSI, Nanofabric, Placement, Assign- ment. 1. INTRODUCTION For the past decades, microelectronic fabrication has been the state-of-the-art technology in semiconductor industry. However, feature size scaling in CMOS has led to many im- plications and manufacturing difficulties. Meanwhile, A new trend is emerging for combining the flexibility and high fab- rication yield advantages of CMOS technology with nanome- ter scale molecular devices. A self-assembly of two-terminal nanodevices with nanowire crossbar fabrics, would enable high functional density and sustain acceptable fabrication costs. Likharev and Strukov [1] introduced hybrid semicon- ductor/nanowire/molecular integrated circuits called CMOL, which use two levels of perpendicular nanowires as cross- bar interconnection on top of inverter-based CMOS stack. Likharev and his colleagues have shown possible applications of CMOL in field programmable gate arrays (FPGA) [2], neuromophic CrossNets [3], and in memories [4]. Recently, several proposals were introduced for cell place- ment on FPGA-like CMOL architecture. Likharev et al uti- lized existing FPGA CAD tools to perform placement on 4 × 4 tile-based version of CMOL [5, 2] and used reserved routing cells and recursive routing algorithm for inter-tile routing. Instead of working at tiles level, Hung et al [6] en- coded the CMOL cell assignment as a Satisfiability problem at cells level, where placement solution was found when all Boolean constraints are satisfied. However, when circuits sizes increased the computation time became exhibitant Previous attempts to use sub-optimal search heuristics are reported in [7, 8, 9]. Genetic Algorithm (GA) [7] was used with two dimensional block PMX crossover operator and mutation, where the fitness function evaluates the Man- hattan distance between connected cells. A more elabo- rate work was reported in [8]; where Memetic computing approach (MA) was used by combining Genetic Algorithm and Simulated Annealing (SA) local-based search heuristic. SA was used to enhance GA offsprings by local improve- ment search. Hung et al [9] extend their work on Memetic approach by integrating self-learning operators using La- grangian Multiplier (LRMA), results reported are promis- ing, however, more computations are needed for penalty up- 21