International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 03 Issue: 05 | May-2016 www.irjet.net p-ISSN: 2395-0072 © 2016, IRJET ISO 9001:2008 Certified Journal Page 2601 EFFICIENT IMPLEMENTATION OF CASCADED IIR FILTER DESIGN AND A PARTITION MULTIPLIER Aarti, Dr. P. Venkataratnam PG student, VTU Extension Centre, UTL Technologies Limited, Bengaluru Professor, VTU Extension Centre, UTL Technologies Limited, Bengaluru ---------------------------------------------------------------------***--------------------------------------------------------------------- Abstract -This paper proposes a beneficial VLSI design for cascaded arrangement of a higher order IIR filter, which can be used in DSP applications like equalizer, loud speakers etc. The proposed configurable 6th order IIR design is arranged with three biquad filters. The same is utilized to perform one sixth order or three second order or one fourth order and one second order calculations in parallel.A multiplier is one of the key equipment pieces in most advanced and superior frameworks, for example, IIR channels, advanced signal processors and microchips and so on. With advances in innovation, numerous analysts have attempted and are attempting to plan multipliers which offer both of the accompanying rapid, low power utilization, normality of design and henceforth less area or indeed, even mix of them in multiplier.So in this paper we show another idea for fast multiplication of two numbers that avoids the overhead of long carry chains. Segment adders and multipliers can be a traded off and can be adopted based on the application demand. Key Words:IIR filters, Configurable design, Multipliers. 1.INTRODUCTION Digital filters are necessary parts of numerous advanced signal processing frameworks, including control systems, systems for sound and video processing etc. Digital filters [2] are used to remove undesirable content of the digital signal. The infinite impulse response filter can be represented using the equation (1). The coefficients are given by ak and bk and M and N define the order of the filter. In this work we take M and N as equal (M=N=6) (1) As we understand from the equation the operation of filter involves repetitivemultiplications and additions so we introduce an effective multiplier thatavoids long chains of carry. Parallel multiplication algorithms have been presented in [4],[5].The proposed multiplieris better than the present multipliers while achieving better performance only with an acceptable increase in the area. In this new assembly for multiplier inputs are parted into segments. Products are computed with no carries between partitioned segments of numbers. Component adders and multipliers to be used can weighedaccording to the application.The Dadda Tree multiplier is thought to be one of the speediest multiplier usages. Wallace Tree multiplier is like Dadda yet involve bigger area relatively. The speed offered by Dadda and Wallace multipliers comes at the expense of extra area. The proposed multiplier consequently offers a tradeoff amongst area and speed. 2. ThePROPOSED IIR FILTER The proposal of biquad filter used in the arrangement isshown in the figure (1). Here b0, b1, b2, a1 and a2 are filter coefficients. The input and output signal example qualities are spoken to as x(n) and y(n) separately. Fig. 1. Proposed IIR filter design Here multiplexers assume the significant part, which choose the proper input/yield signal example values and coefficients for every clock cycle. The condition (2) demonstrates the second order IIR channel operation. (2)