International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 03 Issue: 02 | Feb-2016 www.irjet.net p-ISSN: 2395-0072 © 2016, IRJET | Impact Factor value: 4.45 | ISO 9001:2008 Certified Journal | Page 1340 A survey report on mapping of networks Ms.Mitali V. Chindhalore 1 , Ms.Dipalee M.Kate 2 1 M.Tech Student,Priyadarshani Bhagwati College of Engineering,Nagpur 2 Assistant Professor,Dept.of Electronics and communication, Priyadarshani Bhagwati College of Engineering,Nagpur,Maharashtra,India Abstract-This paper deals with a review of all the researches made on the topic of Network-on-Chip. This is basically a concept of hybriding a huge complex network to a small extent. This is a more promising approach compared to the traditional ways of designing. We are going to enhance the characteristics with the help of newly created network especially the critical of switching mechanisms[1]. Energy consumption of On Chip Networking influenced by mapping of Intellectual Property and this servers the advantage of the new created system. Even though the space optimization tells the system to be more advanced and with additive features. Keywords: Network-on-chip, mapping, communication networks, switching, virtual circuit. 1. INTRODUCTION The day by day advancement in technology give birth to this new valuable concept which thus optimize many features in it. Traditionally way of embedding the multicore architectures and conventional bus communication and crossbar interconnections are thus altered as they were bounded within their bandwidth[1]-[3]. Because of routing in packet switched and circuit switched the latency and energy is lower; so as to overcome this lower latency even some authors proposed the intermingle of virtual circuit switching in that. Not only the optimizing of mapping but also the mapping of communication onto different switching mechanisms. [3]Considering the cases of conventional communications, packet switched NoC came along with the advantage of bandwidth and flexibility to the much higher extent. In the circuit switched connection, switch traversal is required. In this paper, we are investigating the pre-research done on the related topic in prier topics and in the later part of the paper it will say about the work what we are doing and upgrading relatively. 2.RELATED WORK Already there is a huge literature body which has been discussed on this topic of mapping of networks based on On-Chip architectures. In [4], Murali et al. gone with the idea of fast algorithm, called as NMAP, for the purpose of mapping the applications onto a NoC mesh architecture under the concentrated spot of bandwidth. Hu et al[5], focused on the minimization of the usage of energy and has used this very beneficial approach of branch-and-bound algorithm so as to solve these problems. In[6], the problem of mapping latency is