International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 03 Issue: 01 | Jan-2016 www.irjet.net p-ISSN: 2395-0072 © 2016, IRJET | Impact Factor value: 4.45 | ISO 9001:2008 Certified Journal | Page 531 Automatic Analyzing System for Packet Testing and Fault Mapping Mr. Shrikant B. Chavan 1 , Prof. Soumitra S. Das 2 1 Researcher, Department of Computer Engineering, Dr. D. Y. Patil School of Engineering, Pune, India 2 Guide and HOD, Department of Computer Engineering, Dr. D. Y. Patil School of Engineering, Pune, India ---------------------------------------------------------------------***--------------------------------------------------------------------- Abstract - now a day’s Networks are getting larger and more complex, hence network admin depend on normal tools such as ping and to traceroute debug the problems. Automated and systematic approach for testing and debugging networks called DzAutomatic Analyzing System for Packet Testing and Fault Mappingdz. This system read router configurations and generates a device-independent model. This model is used to generate a minimum set of test packets to check every link in network check every rule in the network. Test packets are sent periodically, and detected failure trigger a separate mechanism to localize the fault. This model can detect both functional testing and performance testing problems. This proposed to use symbolic execution a technique prevalent in compilers to check network properties more general than basic reachability. the key idea is to track the possible values for specified fields in the packet as it travels through a network. Keywords:Dataplane analysis, network troubleshooting, test packet generation, Network, Monitoring Functional Testing, Performance Testing 1.INTRODUCTION It is difficult to debug systems. Day by day system architects grapple with switch misconfiguration, fiber cuts, flawed interfaces, mislabeled links, programming bugs, irregular connections, and different reasons that cause systems come up short totally. System architects to execute down bugs utilizing the most well-known devices (e.g., Ping , Traceroute ,SNMP,and Tcpdump) and track main drivers utilizing a mix of accumulated shrewdness . Debugging of systems is just getting to be difficult to systems are getting greater (current server farms may contain 10 000 switches, a grounds system may serve 50 000 clients, a 100-Gb/s long term connection may convey ͳͲͲ ͲͲͲ flowsȌ and are getting more confounded (with in excess of 6000 RFC, switch programming is focused around a large number of lines of source code, and system chips likewise contain billions of entryways). It is a ponder that system specialists have been marked "experts of many sided quality". For that Consider a same.[1] Example 1: Suppose a router with a faulty line card starts dropping packets silently. Admin, who administers 100 routers, receives an ticket from several unhappy users complaining about connectivity. First Admin examines each router to see if the configuration was changed recently and concludes that the configuration was untouched [2]. Next, Admin utilizes his insight into topology to follow the broken gadget with ping and tracerout charge. At long last, he calls an associate to supplant the link. That the two most regular reasons for system disappointment are equipment disappointments and programming bugs, and those issues distinguished themselves both as achieve capacity disappointments and throughput/inertness debasement. to test the liveness to give backing to topology .The instrument can likewise naturally produce parcels to test execution attestations, for example, parcel inactivity.[2] 2.RELATED WORK Present day machine systems can be isolated into the information plane and the control plane. The information plane comprises of various interconnected switches, each one contains sending decides that focus the flow of parcels. For instance, the sending lead in an Ethernet switch takes a gander at a bundle's end of the line MAC address, and chooses its next port. [6]. On top of the information plane is the control plane that runs directing conventions, for example, OSPF or BGP. The control plane populates the information plane with sending tenets focused around its worldwide system learning. The objective of information plane testing incorporates two sections: 1) checking sending guidelines rightness given topology and strategy (e.g., the back-end database can't converse with the front-end web server straightforwardly); 2) confirming system execution given the administration level assertion, which is an agreement between the system administration supplier and its clients. Fig. -1 Plane Testing The disastrous substances of system operation make programmed, precise information plane troubleshooting a need. Nonetheless, there is more than one approach to