ISSN: 2278 – 7798 International Journal of Science, Engineering and Technology Research (IJSETR) Volume 2, No 6, June 2013 1237 www.ijsetr.org Arbitrary Density Pattern (ADP) Based Reduction of Testing Time in Scan-BIST VLSI Circuits G. Naveen Balaji S. Vinoth Vijay Abstract— Test power reduction done by Arbitrary Density Patterns (ADP) in which the dynamic usage of the WRP and TDP under adaptive switching of clock is used. Weighted random patterns (WRP) and transition density patterns (TDP) can be efficiently used to decrease test length with increased fault coverage in scan-BIST circuits. New test pattern generator is designed to generate weighted random patterns and controlled transition density patterns to enable efficient scan-BIST applications. We attain decrease in test time without sacrificing fault coverage while preserving test power limits by dynamically adjusting the scan clock, which is provided by a built-in hardware monitor of transition density in the scan register. Keywords— ADP, TDP, WRP, BIST, inactivity monitor I. INTRODUCTION With the growth in size, the number of test vectors required to test them has also improved. The time taken to test a chip is the product of the number of test vectors used and the time required to apply each vector in the CUT. As the number of test vectors rises, the time for applying them also increases. Since classy ATE is used to examine these chips, the cost per chip is increased with increase in test time. There is therefore increasing concern about the time essential to apply these test vectors. Due to progression of technological expertise circuit size has increased which naturally entitles longer test time. On the other hand, the test process results in greater power dissipation in the circuits compared to the power dissipated in the standard mode of the circuit. ADP consists of WRP and TDP. Weighted random patterns (WRP) have been used before to reduce test length for combinational circuits. Proper range of the input probability can raise the effectiveness of test vectors in spotting faults, causing test time reduction. Complete scan proposal is a common plan for testability (DFT) method in which flip-flops in the circuit are connected together such that input vectors are shifted in and circuit responses are shifted out serially through the scan chains. The flip-flops serve as sockets of controllability and observability, thus accumulating the fault coverage. ------------------------------------------------------------------------- G. Naveen Balaji, PG Scholar, Electronics and Communication Engineering, Madha Engineering College, Chennai, INDIA. 8682010042 S. Vinoth Vijay, PG Scholar, Electronics and Communication Engineering, Madha Engineering College, Chennai, INDIA. 9500277434 Transition density patterns (TDP) are largely used for sinking the power consumption during test. Transition density for a signal or a circuit was initially defined for assessing the dynamic power as the number of signal transitions per unit time. II. OBJECTIVE Analyse the effect of ADP on fault coverage. (Arbitrary density pattern = Weighted random pattern + Arbitrary density pattern). Organize an effective test generation process using the information from the analysis. Adjust the scan frequency to the transition density for power constrained testing. New test pattern generator with the capability of producing ADP has to be done. Adjust the scan frequency according to the transition density for a scan- BIST circuit to boost up the test in multiple scan chains. Deployment of an adaptable transition density test pattern generator in a BIST circuit that is capable of producing pre- designated transition density vectors. Reduction of test application time is attained by adapting the scan clock to the pre-selected transition density. III. BACKGROUND A. Scan Design Sequential circuits are tougher to test than combinational circuits. This is because the existence of memory elements such as flip-flops, as shown in Figure 1, which creates internal states during circuit operation. An exhaustive test would involve application of all probable input vectors at all possible states of the memory elements. If a circuit has n inputs there will be 2n possible input combinations. As n increases the number of possible input vectors increases exponentially. This type of occurrence is even more severe for sequential circuits. The DFT technique that improves testability of sequential circuits is designed as a scan design or its partial scan dissimilarities. Here the sequential circuit is newly designed so that it can operate in test mode separately. When the circuit is in test mode, the flip-flops in the circuit are chained together to form one or more shift registers. The shift registers so formed is also called as scan path. The scan path is responsible for the circuit switching activity. The flip-flops serve as a point of controllability and observability.