www.iaset.us editor@iaset.us IMPLEMENTATION OF LOW POWER EXPLICIT PLUSE- TRIGGERED FLIPFLOP BASED ON SIGNAL FEED THROUGH SCHEME NIHAR RANJAN JENA, SUBHARAJIT JENA & ANANYA DASTIDAR Department of Electronics and Communication Engineering, Centre for Advance PG studies, BPUT Rourkela, Odisha, India ABSTRACT Power consumption is a key design factor in many circuits. We can say low power concept is a skeleton of electronic industry. The requirement of low power is for consideration of power dissipation and the greatest challenge regarding area and circuit performance. A low power flip-flop design structure is explicit type pulse, trigger and a modified single phase clock is used for signal feed through the scheme. Pulse-triggered FF (PFF) is a single-latch structure that is more advantageous than the conventional transmission gate (TG) and master–slave based FFs in high-speed applications. In this work we have implemented various edges triggered flip-flop and studied their behaviour. We then proposed an Efficient P-FF design solves the long discharging path problem in case of conventional explicit type pulse-triggered FF (P-FF) and achieves better speed and power performance. Based on post-layout simulation results using Micro wind CMOS 90-nm technology, the Efficient P-FF design outperforms the conventional P-FF design in data-to-Q delay. In the meantime, the performance edges on power metrics respectively. Various simulation results based on CMOS 90-nm technology reveals that the Efficient P-FF design is power efficient when the pulse generator is shared with multiple FF’s. A better D-to-Q Delay is achieved. Both cadence virtuoso (90 nm technology) and micro-wind version 3.0.0 were used in the study and implementation of the circuits in this work KEYWORDS: PFF, Flip-Flop, SDFF, HLFF INTRODUCTION Today's technologies make possible powerful computing devices with multimedia capabilities. Consumers' attitudes are gearing towards better accessibility and mobility. Their desire has caused a great demand for an ever increasing number of portable applications requiring low-power and high throughput. Low power VLSI systems are exponentially used in mobile devices, instrument for biomedical, signal and systems. In general purpose electronics systems such as personal computers, cellular phones, or handheld computers, i.e., tablets PC, we may find numerous Integrated Circuits (IC), placed together with discrete components on a Printed Circuit Board (PCB). The integrated circuits appearing in this figure have various sizes and complexity. The circuit consists of a microprocessor which is called as the heart of the system that is only chip which includes millions of transistors. The push for smaller size, reduced power supply consumption and enhancement of services, has resulted in continuous technological advances, with possibility for ever higher integration For example, notebook and handheld computers are now made with competitive computational capabilities as those found in desktop machines. Equally demanding are personal communication applications in a pocket-sized device. In these applications, not only voice, but data as well as video are transmitted via wireless links. It is important that these high computational capabilities are placed in a low-power, portable environment. The weight and size International Journal of Electronics and Communication Engineering (IJECE) ISSN(P): 2278-9901; ISSN(E): 2278-991X Vol. 6, Issue 5, Aug- Sep 2017; 7-16 © IASET