IEICE TRANS. FUNDAMENTALS, VOL.E88–A, NO.4 APRIL 2005 1031 PAPER A Low Latency Asynchronous FIFO Combining a Wave Pipeline with a Handshake Scheme Jeong-Gun LEE † , Suk-Jin KIM † , Student Members, Jeong-A LEE ††a) , Nonmember, and Kiseon KIM † , Member SUMMARY This paper presents a new asynchronous FIFO design to reduce forward latency in a linear structure. The operation mode for each cell can be reconfigured dynamically as either of the two schemes, wave pipelining or handshaking, according to the data flow in the FIFO. The adoption of wave pipelining to the conventional self-timed FIFO can reduce the overhead of the handshaking as well as latching control in each stage. Initial pre-layout simulations indicate about two times of improvement on latency performance over a state-of-art asynchronous FIFO, while retaining its throughput. key words: asynchronous FIFO, wave pipeline, linear structure, forward latency, throughput 1. Introduction A FIFO is commonly used as a buffer to smooth out bursty traffic between a data producer and a consumer. In addi- tion, the independent interfaces of its input and output can provide a solution for bridging clock domains. In an asyn- chronous system, most of FIFOs are implemented using a ripple or linear structure that exploits local communications between cells, whereas FIFOs in a clocked system are usu- ally implemented with a ring structure using read and write pointers with a global clock [1]. It is note worthy that asynchronous linear FIFOs are useful in many asynchronous as well as clocked systems due to their simple and modular design. The recent Sun UltraSPARC  IIIi processor includes many asynchronous linear FIFOs to transfer data from synchronous RAM into the processor clock domain [1]. Two key performance measure of the asynchronous FIFO are forward latency and the cycle time. Forward la- tency is the time for a data item to pass an empty cell, while the cycle time is the time interval between two ad- jacent data items at maximum speed. The linear FIFO can provide steady throughput, however, it increases forward la- tency because it adds sequential data movement inside the FIFO. Therefore, long latency of the FIFO may have critical impact on the overall performance of systems. Alternative approaches to building low latency asyn- Manuscript received May 10, 2004. Manuscript revised October 3, 2004. Final manuscript received December 24, 2004. † The authors are with the Department of Information and Communications, Gwangju Institute of Science and Technology, Gwangju, 500-712, Korea. †† The author is with the Department of Computer Engineering, Chosun University, Gwangju, Korea. a) E-mail: jaLee@chosun.ac.kr DOI: 10.1093/ietfec/e88–a.4.1031 chronous FIFO have been proposed [2]–[5]. These FIFOs reduces the number of data movement by modifying its structure from a standard linear one (for instance, a parallel, a tree,a squared, and a folded structure). Although the con- trol circuitries of these FIFOs brings a small increase in area, the overhead of the overall FIFO can be significant when a wide datapath is applied. A focus of the proposed asynchronous FIFO is to tar- get low latency while retaining high throughput and sup- porting a small area of the linear structure. To reduce for- ward latency of the FIFO we adopt the well-known wave pipelining technique [6] to a conventional self-timed FIFO. Subsequently, the FIFO is configured dynamically as wave pipelining mode for a latency-critical situation (e.g., all cells in a FIFO are empty), and as handshake pipelining for a throughput-critical situation (most of cells are full). Since neither handshaking nor latching control is required during wave pipelining, the proposed FIFO can reduce forward la- tency in the wave pipelining mode. On the contrary to the synchronous wave pipelining, furthermore, balancing of the data path delays is relatively easy since the FIFO does not include the combinational logic inside. Moreover, the area overhead of the FIFO is only caused by the added control circuitry thanks to the linear structure. The rest of the paper is organized as follows. Sec- tion 2 introduces the basic idea and behavior of the proposed FIFO. The detailed implementation issues are discussed in Sect. 3 and the simulation results are shown in Sect. 4. Fi- nally we draw conclusion in Sect. 5. 2. The Basic Idea for Improving Latency Performance The basic idea of the proposed FIFO is “to adopt wave pipelining in cells where a data item can advance forward without handshaking.” Basically, the asynchronous FIFO stores the full or empty state of a cell to a flip-flop for hand- shaking with adjacent cells. The data item entering the FIFO can propagate through empty cells along with its cor- responding request without handshaking or latching just like a wave until it meets the cell whose state is full. Then, the corresponding data item is saved to the empty cell be- fore the full cell while making it a full state as well. After stopping wave propagation, the data movement is controlled by a handshake protocol as a conventional asynchronous FIFO does. Since neither handshaking nor latching control is required during wave pipelining, we can improve latency performance of the proposed FIFO. Note that the wave is Copyright c  2005 The Institute of Electronics, Information and Communication Engineers