International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 04 Issue: 10 | Oct -2017 www.irjet.net p-ISSN: 2395-0072 © 2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 448 Netlist Optimization for CMOS Place and Route in MICROWIND Mahesh G. Jaiswal 1 , Varsha Bendre 2 , Vinay Sharma 3 1 PG Scholar, Dept. of ME VLSI & Embedded, PCCOE Pune, Maharashtra, India 2 Assistant Professor, Dept. of ME VLSI & Embedded, PCCOE Pune, Maharashtra, India 3 Technical Director, Ni Logic Pvt. Ltd. Pune, Maharashtra, India ---------------------------------------------------------------------***--------------------------------------------------------------------- Abstract - Microwind is a software tool which is used for CMOS IC layout design. The gate level design is created in schematic editor and simulator tool DSCH. The transistor size in the last few decades is shrinking drastically with the rapid advancement of VLSI technology to integrate more number of transistors on a single IC chip. This will indirectly affect the complexity in the placement and routing of the logic devices. And for any tool it is always a challenging task to make an efficient placement and routing of the cells. One of the EDA tool for CMOS design is MICROWIND, which uses a verilog net list generated by a schematic editor DSCH. This paper focuses on improvement in Microwind tool by implementing a logic optimization method for rearranging verilog net list according to interconnect wire nodes and number of logic cells like CMOS inverter, AND, OR etc. gates using MOS at 120nm technology and using FINFETs at 14nm technology. Our algorithm will rearrange net list and cells without reducing the actual transistors count. Therefore only the total numbers of metal layers, area of chip and interconnect delay etc. will get reduced to produce an optimum design. Key Words: Area, DSCH, Frontend-Backend design, Logic Synthesis, MICROWIND, Net list, Optimize, Placement, Routing, etc. 1. INTRODUCTION VLSI is the process of combining thousands of transistors into single Integrated Circuit (IC) chip. Interconnecting wires length increases with the increase in transistors in the circuit. It is difficult to reduce the capacitive and resistive effects which have an impact on time delay. The interconnecting wires also have fixed area and width making length as the only controllable parameter. Due to this there is a need of optimization techniques in VLSI design. In a Hardware Description Language like Verilog or VHDL, a net list is a description of all the devices or gates and all of the connections or wires between each device. In its simplest form, a net list consists of a list of the terminals (i.e. "pins") of the electronic components in a circuit and a list of the electrical conductors that interconnect the terminals. A net is a conductor that interconnects two or more component terminals. [6] The objective of this paper is to develop an optimization logic that will automatically rearrange the verilog net list and create an efficient layout of the design in Microwind program. For the simulation purpose and observing the result of net list optimization logic, DSCH and MICROWIND tool is required. The basic idea is to optimize the net list generated after successful design of any analog, digital or sequential circuit in schematic editor tool i.e. DSCH. According to that net list a layout is generated in MICROWIND tool which should be as much efficient to design a chip. This must be optimized in concern with area, interconnect, costing, metal routing etc. To design an IC, VLSI IC design flow must be followed by the designer. The ASIC design flow is as shown in fig. 1. This design flow is mainly divided into two parts i.e. Frontend and Backend. This fig 1 shows few steps of the ASIC design. This paper introduces an optimization logic which must be applied in between Gate Level Net list and Floor planning step. A gate-level net list is a description of the circuit in terms of gates and connections between them, which are made in such a way that they meet the timing and power requirements. The actual placement of all logic cells is done in the way of gate level net list is arranged. Here in MICROWIND, a verilog net list decides the floor planning, placement of cells and their input-output routing. Fig 1: VLSI IC Design Flow After compiling the verilog net list in MICROWIND, the floor planning, Partitioning, Placement and routing steps are done at the backend to produce a CMOS layout. Placement of cells and routing within the cells is becoming a difficult task for the designer as number of small sized transistors increases. To make this backend process as well as CMOS layout more efficient, optimization logic must be applied before the floor planning and placement steps. For physical layout structure and time optimization the various techniques like mapping, cell sizing, buffering and logic restructuring etc. can be