Flow-based Computing on Nanoscale Crossbars: Design and Implementation of Full Adders Zahiruddin Alamgir, Karsten Beckmann and Nathaniel Cady SUNY Polytechnic Institute 4403 NanoFab East 257 Fuller Road Albany, NY 12203 Email: ncady@sunypoly.edu Alvaro Velasquez and Sumit Kumar Jha Computer Science Department University of Central Florida 4000 Central Florida Blvd Orlando, FL 32765 Email: jha@eecs.ucf.edu Abstract—We present the design and implementation of a full adder circuit that exploits the natural flow of current through nanowires and More-than-Moore nano-devices in two dimensional crossbars. We evaluate the speed and energy efficiency of our design and compare it to equivalent one-bit adder designs using CMOS and nanoscale memristors. Our memristive full adder circuit has been shown to be an order of magnitude faster and more energy-efficient than equivalent CMOS designs. Our circuit is an order of magnitude more compact that equivalent CMOS designs. We also argue that our design occupies less area and is faster than competing memristor designs. Index Terms—Memristor, Crossbars, Adders, Sneak Paths, Digital Computing, Nanowires, Nanoscale Devices. I. INTRODUCTION The exponential growth in the performance of computing systems over the last forty years has climaxed with a 10,000- fold increase in individual processor speeds over the last two decades of the 20th century [1]. During this period, three things have remained invariant: (a) The increase in performance has come largely from the shrinking of the feature size of CMOS devices [2] reducing the voltage requirement of the circuit and permitting an increase in the clock frequency without exceeding the power budget. (b) John Von Neumann’ s computer architecture [3] has been successfully implemented using hierarchical memory units and one or more processor units communicating using standardized on-chip interconnects and off-chip buses. This Von Neumann gap between processors and memories has traditionally been bridged using increasingly complex memory hierarchies. (c) There has been a clear separation between the software and hardware stacks [4] achieved using a series of optimizing compilers for standardized languages with different back- ends [5] and a strongly preserved backward-compatibility of the x86 instruction set over several generations of processors. Thus, the increasing design complexity involved in rapidly improving computing performance, such as deep and speculative pipelining, not yet been achieved. The worldwide information technology industry has grown to a size of more than $3 trillion largely because of the exponential growth in computing capacity and the sustained consistency of the programming model across multiple generations of processors. The end of Dennard scaling threatens this exponential growth and the societal expectations of faster cyberinfrastructure from scientists and the public at large. In this paper, we respond to the crisis caused due to the end of Dennard scaling by demonstrating that the flow of current through nanoscale crossbars can be used to perform addition in a fast, energy-efficient, and compact manner. We evaluate the speed and energy efficiency of our design and compare it to equivalent one-bit adder designs using CMOS and nanoscale memristors. Our memristive full adder circuit has been shown to be an order of magnitude faster and more energy-efficient that the equivalent CMOS design. Our circuit is also an order of magnitude more compact that equivalent CMOS designs. Our results suggest a promising direction towards the development of next generation, energy efficient, and compact computing devices. II. RELATED WORK A. Addition Using Memristive ‘Stateful’ Logic Operation Fig. 1 (left) Schematic cross-section of a memristor used in this work. (right) SEM View of a 12x12 memristor crossbar array. Crossbar arrays were fabricated at SUNY Polytechnic Institute on 300 mm wafers using a modified IBM 65nm 10LPe process flow