IJSRD - International Journal for Scientific Research & Development| Vol. 5, Issue 08, 2017 | ISSN (online): 2321-0613 All rights reserved by www.ijsrd.com 75 Design and Implementation of Low Delay Look Ahead Adder and Ripple Adder Samrat Kumar Singh 1 Deepak Kumar 2 1 M. Tech. Scholar 2 Assistant Professor 1,2 Department of Electronics & Communication Engineering 1,2 VIST Bhopal India Abstract— In recent years, a lot of attentions have been attracted by the reversible logic due to the characteristic of zero energy dissipation. In this paper, the author proposed a 16 bit carry look-ahead adder is constructed by four 4 digits groups based on the theory of reversible logic, which has the advantages of theoretical zero power dissipation and high efficiency. This paper focuses on the implementation 16 and bits of highly optimized area efficient Ripple carry adder (RCA) and Carry look ahead (CLA) adders. Ultimately, we can establish that the Carry look ahead adders are so greatest among all the formerly active designs. All these processes will be Simulated & Synthesized on the ISE Xilinx 14.7 software. Key words: Adder, Ripple Carry Adder, Carry Look-Ahead Adder, Carry Select Adder VHDL Code I. INTRODUCTION With the increasing importance of energy dissipation in integrated circuits, the reversible logic implementations gain in prominence as a way to reduce power since irreversible computing is one of the most significant factors to generate energy dissipation. By the Landauer's principle, each bit of information lost will generate kl1n2 joules of heat energy, where T stands for the absolute temperature at which computation is performed and k is Boltzmann's constant[1][8] so how to avoid information lost is an efficient way to decline the energy dissipation in digital integrated circuits. High-speed adder is the Necessary component in a data path e.g. Microprocessors and a Digital signal Processor. For adding two binary numbers, there are several adder Structures based on different Design ideas. There are many binary adder architecture ideas to be implemented in such applications. The easiest type of parallel adder to build is a ripple carry adder, which uses a Chain of one bit full adder to generate its output. The Ripple Carry Adder (RCA) gives the most compact design but Takes longer computation time. The time critical Applications use Carry Look-ahead scheme (CLA) to derive Fast results but lead to increase In area. In mobile electronics, falling area and influence utilization are Solution factors in growing portability and sequence life Even in servers and desktop Computers, power an important design constraint [1] II. RIPPLE ADDER Ripple carry adder A ripple carry adder is a digital circuit that produces the arithmetic sum of two binary numbers.[4] may be capable of constructed with full adders connected in cascaded through the carry output beginning every full adder associated to the carry input of the next full adder in the chain the interconnection of four full adder (FA) circuits to provide a 4-bit ripple carry adder observe from so as to the input is beginning the accurate side because the first cell traditionally represents the least significant bit (LSB). Bits and in the figure represent the least significant bits of the numbers to be added. The sum output is represented by the bits Show in fig. 1Below [10] Fig. 1: Full adder III. CARRY LOOK AHEAD ADDERS (CLA) The Enter to speed up adding up is influential the carry in to the soaring order bits sooner. There is assortment of scheme to expect the carry so that the nastiest case scenario is a function of the log2 of the number of bits in the adder. These preventative signals are quicker since they go throughout fewer gates in succession, but it takes many more gates to anticipate the proper carry a key to understanding fast-carry schemes is to remember that, unlike software, hardware executes in parallel whenever Inputs change Look-Ahead Adder a Carry Look-Ahead adder (CLA) is a type of adder used to improve speed by reducing the amount of time required to determine carry bits. It can be contrasted through the simpler, but frequently slower, ripple carry adder intended for which the carry small piece is designed alongside the sum bit, and each bit must wait until the previous carry has been calculated to begin calculating its own result and carry bits. Show in fig.2. Fig. 2: Carry Look-Ahead Adder The Carry Look-Ahead Adder calculates one or additional carry bits before the sum, which condense the wait time to estimate the result of the larger value bits. Consider a full adder circuit as shown in Figure 2 Pi = Ai Bi (1) Gi = Ai Bi (2) Where, Gi is carry generate and Pi is carry propagate. The output sum and carry can be expressed as Si = Pi Ci (3) Ci+1 = Gi +Pi Ci (3) Gi produce on carry at what time both Ai and Bi are one, despite of the input carry. Pi is connected with the propagation of the carry from Ci to Ci+1. Now the Boolean