The 5th International Conference on Electrical Engineering – Boumerdes (ICEE-B) October 29-31, 2017, Boumerdes, Algeria. A Flexible Network on-Chip Router for Data-Flow Monitoring Mohammed Amine Meghabber 1 ; Abdelkader Aroui 1 ; Lakhdar Loukil 1 ; Abou El Hassan Benyamina 1 ; Kamel Benhaoua 1 ; Toufik Djeradi 2 {meghabber.mohammed; aroui.abdelkader}@edu.univ-oran1.dz; {loukil.lakhdar; abouelhassan.benyamina; benhaoua.kamel}@univ-oran1.dz; TDjeradi@slb.com 1 Computer Science Department, University of Oran 1, Algeria 2 Schlumberger Integrated Solutions, Houston, USA. Abstract— The Network on-Chip (NoC) is considered as an emerging technology for distributed embedded systems which is proposed as an alternative interconnection solution in Mutli- Processors System on-Chip (MPSoC). This paper proposes a graphical toll that allows researchers to generate and configure quickly their Network on-Chip in the hope to evaluate easily their contributions in no time. Unlike major existing simulators which are developed in hardware language description and make debugging very difficult, this high-level framework helps software designer, who need simpler means, to properly build mapping and scheduler algorithm then validate their contributions. This proposed toll is open source and extensible. The provided conceptual details allow users to efficiently create, validate their real scheduler and mapper as well as integrate it easily. Keywords- Embedded Systems, Network on-Chip, Simulation, Router, Wormhole, Monitoring. I. INTRODUCTION As the technology advances, the number of processors inside chip grows. In last three decades, the hardware (processors) evolution was exponential and the Moor law, that states: “the number of transistors on an integrated circuit doubled every year”, reached their physical limits [1] because the heat dissipation and the power consumption became major factors. Such bottlenecks encourage the design architects to design novel system on-chip architecture to overcome these limits and move toward Network on-Chip paradigm [2]. Inspired from the classical network, the NoC becomes an emerging technology and promising solution to overcome these walls by proposing a communication paradigm [2]. When the classical multiprocessors shared bus architectures reached their limits (cannot scale very well when adding new node to the system), the NoC overcomes this problem by offering high scalability and improved parallelism. Many industrials have followed this route and developed commercial NoCs such as TeraFLOPS on-chip network, developed by Intel [3] and TILEPro64 developed by Tilera [4]. On the other hand, many embedded applications, such as aerospace domain [5], are complex and require high performance in term of lower energy consumption and real time constraints. These applications exchange huge volume of messages when executing their tasks on Processing Element (PE), which means, they need platform that offers an efficient underlying communication infrastructure similar to what Network on-Chip offers. PE NI R PE NI R PE NI R PE NI R PE NI R PE NI R PE NI R PE NI R PE NI R PE NI R PE NI R PE NI R PE NI R PE NI R PE NI R PE NI R Router Processor Element Network Interface Physical Link R PE NI Figure 1. 2D-mesh Network On-Chip In this work, we are motivated to perform a detailed comparison on the existing NoC simulators (real time or not). We will discuss tools that facilitate execution and debugging applications that may require rebooting and re-running the code when using hardware emulators. Unlike other emulators, especially implemented on FPGA, where users make long time to load such configuration, minutes to hours to compile this configuration and hours to months to create new configurations considering the limited scalability, this work tries to present an open source extensible simulator that supports different application models which helps designers to build their techniques (scheduler and mapper) and validate them very easily. The same for Hardware architects who can develop novel designs (switching, routing, arbiters…) and integrate them to the simulator in an optimal time. The framework has a graphical layout which allows users to monitor the execution in real-time and locates routers that suffer from congestion. At the end of simulation, results are stored in an Extensible Markup Language (XML) file in way that describes the simulation behavior cycle-by-cycle illustrating router buffer states, traffics, and latency of different packets over the platform. This XML file can be also used as input file for the simulator to reply the execution of the application and allows users to set “Pause” at any time (any cycle) to observe a specific behavior then resume execution “continue”. By providing the simulator model pattern, the design details, as described in Section 4 and the graphical layout that monitors application’s behavior, we bring together the advantages of others (Table I). This work has been supported by the PHC TASSILI Program via the research project n° 14MDU917