Power Consumption Optimization Technique in ACS For Space Time Trellis Code Viterbi Decoder Mohd Azlan Abu 1,2,a , Harlisya Harun 1,3 , Mohammad Yazdi Harmin 1 and Noor Izzri Abdul Wahab 4 1 Department of Aerospace Engineering, Faculty of Engineering, University Putra Malaysia, 43400 Serdang, Selangor, Malaysia 2 University Kuala Lumpur British Malaysian Institute, 53100 Gombak, Selangor 3 University Kuala Lumpur Malaysian Institute of Aviation Technology, 43900 Dengkil, Selangor 4 Department of Electrical and Electronic Engineering, Faculty of Engineering, University Putra Malaysia, 43400 Serdang, Selangor, Malaysia a mohdazlan@unikl.edu.my Keywords: Power Consumption, Space Time Trellis Code, Viterbi Decoder Abstract. To provide fast digital communications systems, energy efficient, high-performance, low power is critical for decoding mobile receiver device. This paper proposes a low power optimization techniques in the Add Compare Select (ACS) unit for Space Time trellis codes (STTC) Viterbi decoder. STTC Viterbi decoder is used as a reference case. This paper discusses about how to lower the power in the ACS architecture, to optimize the Viterbi decoder STTC in reducing the total power consumption. Based on the results of design and analysis, power consumption Viterbi decoder modeling, low power system for STTC Viterbi decoder is proposed. Design and optimization of ACS unit in STTC Viterbi decoding is done using Verilog HDL language. Power analysis tools in the software Altera Quartus 2 is used for the synthesis of total system power consumption. Optimization strategy showed an increase of 83% power reduction compared to previous studies. Introduction In recent years, there has been an increasing complexity of digital portable communications. The 3G, WiFi or LTE air interface with Multiple Input Multiple Output (MIMO) schemes are examples of this trend towards more demand for computational power in the digital baseband, while limiting the impact on power consumption and chip size. In addition, the flexibility needed for new applications, such as Software Defined Radio (SDR) or Cognitive Radio (CR), showing more requirements in flexibility and portability. In the overall complexity of modern digital communication, channel decoding, and more specifically Viterbi decoding, is one of the complex computations and intensive memory components[1]. STTC Viterbi decoding implementation is complex and power consuming. In particular mobile terminal, receiver decoder is the energy constrained applications because it has limited energy resources such as portable devices. The base station is less energy constrained. However, all this application is a real time, and power optimization cannot be achieved with an unacceptable loss in performance. As a result, systems that meet the flexibility, performance and energy objectives, namely energy efficiency, the design must take into consideration[1]. For reasons of flexibility and multipurpose implementation of STTC Viterbi decoders, programmable devices are necessary. Complex Programmable Logic Devices (CPLD) execution is one solution to solve this problem, but it uses more power than specialized hardware for the same task. This is because the structure of the flexible connection, large control and memory used. Instead, the parameterized hardware implementation can meet the constraints of pure power, but cannot be adjusted at the time of programming for applications requiring high Applied Mechanics and Materials Vol. 785 (2015) pp 734-738 Submitted: 2015-01-15 © (2015) Trans Tech Publications, Switzerland Revised: 2015-03-23 doi:10.4028/www.scientific.net/AMM.785.734 Accepted: 2015-04-04 All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, www.ttp.net. (ID: 175.143.97.133-25/06/15,03:42:37)