1 Monolithic 3D Integration of SRAM and Image Sensor Using Two Layers of Single Grain Silicon Negin Golshani 1 , Jaber Derakhshandeh 1 , Ryoichi Ishihara 1 , C.I.M Beenakker 1 , Michael Robertson 2 and Thomas Morrison 2 1 ECTM, Delft Institute of Microsystems and Nanoelectronics (DIMES), Electrical engineering (EWI), TU Delft Feldmannweg 17, 2628CT Delft, The Netherlands n.golshani@tudelft.nl 2 Department of Physics, Acadia University, 12 University Ave., Wolfville, NS B4P 2R6, Canada Abstract— In this paper we report the monolithic integration of two single grain silicon layers for SRAM and image sensor applications. A 12 × 28 silicon lateral photodiode array with a 25_µm pixel size prepared on top of a three transistor readout circuit with individual outputs for every pixel is demonstrated. 6T SRAM cells with two layers of stacked transistors were prepared to compare the performance and area of each cell in different configurations. I. INTRODUCTION Interconnect delay and manufacturing costs involved in the lithography process are two important problems for down scaling of transistors. Three dimensional integrated circuits are the best solution to continue Moore’s law for the next generation of ICs [1,2,3]. As Shown in Fig.1 three approaches have been used to stack the active devices including device level, chip level and wafer level [1,2,3]. Device level or monolithic 3D approach, offers high density interconnects and lower cost compare to the other methods. Fig. 1: Illustration of three approaches for 3DIC, For some particular applications such as artificial retinas, lower area, dense interconnects and parallel processing are required in order to process the large amount of information which comes from the photodiodes. The ability of photodiodes to act as solar cells and lower power consumption for the readout and processing circuits, as well as a flexible substrate to fit the chip between the inner and outer retina, is very important. Monolithic 3D integration using a low temperature µ-Czochralski process is one of the best candidates for artificial retina, high density and high speed SRAMs, and high resolution image sensors applications [4-8]. In this process amorphous silicon is deposited on an oxide layer containing small holes in order to initiate crystallization of amorphous silicon from a seed using an excimer laser. The crystalline grains are around 7_µm × 7_µm in size which is large enough to locate high performance transistors within grains. The fabricated thin film transistors have mobility values of 600_cm 2 /Vs and 300_cm 2 /Vs for nMOS and pMOS transistors, respectively [4-8]. This process is similar to fully depleted SOI process which has the advantages of high speed devices and lower power consumption. In this paper we will detail the fabrication process and the results of SRAM cells and 3T APS (three transistors active pixel sensor) image sensors using this technology with two stacked layers of single grain silicon. II. DESIGN OF SRAM CELLS AND 3T APS SRAM cells and arrays of photodiodes have been designed using two layers of single grain silicon with 2_µm gate length. For 6T SRAM cells, different combinations of access, drivers and pull up transistors have been designed. Table 1 shows the specifications of the different layouts. In this table, area and number of VIAs between the two layers have been compared for different placements. Table 1: Different combinations of access, drivers and pull up transistors for 6T SRAM cells to be placed in two layers Top layer Access and nMOS (1) pMOS (2) nMOS (3) Access and pMOS (4) Bottom layer pMOS Access and nMOS Access and pMOS nMOS Number of VIA interconnects 5 8 10 5 Area 242F 2 128F 2 187F 2 187F 2 Other Advantages No mask for S/D doping No mask for S/D doping Less sensitive to soft errors