IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 6, JUNE 2016 2195 Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence Zhong Guan and Malgorzata Marek-Sadowska, Fellow, IEEE Abstract— Electromigration (EM) greatly affects the long-term reliability of VLSI chips. Not only power/ground lines but also bitlines of SRAM arrays may be damaged by EM. In this paper, we analyze current flow on SRAM bitline, demonstrate that it may suffer EM due to the pulsed dc pattern, and conclude that bitline’s EM reliability can dramatically be worsened by process variation due to a significant increase of subthreshold leakage current. We statistically model the effects of process variation that includes both transistor parameter fluctuation and interconnect line roughness, propose an atomic flux divergence-based current conversion scheme for applying Blech criterion, and develop a procedure for preventing EM failure by modifying the width of bitlines. Considering the effect of bitline width modification on cell stability and performance, we propose a tradeoff between functional and EM failures and indicate an optimal bitline width that maximizes the yield of SRAM arrays. Index Terms—Atomic flux divergence (AFD) and optimum width, electromigration, signal line, SRAM. I. I NTRODUCTION S RAM arrays are essential blocks of microprocessors which occupy a large fraction of a chip area dedicated to data cache. Large and reliable SRAM arrays manufactured with small yield losses are required by the VLSI market today, but manufacturing of reliable SRAM arrays becomes progres- sively more difficult in advanced technologies. In addition, manufactured SRAMs are prone to various reliability effects. Transistor aging effects and their influence on SRAM per- formance have extensively been studied [1]. In [2], transistor failure mechanisms and their effect on SRAM reliability parameters, including cell stability, cell read failures, and cell access time failures, are discussed. In [3], researchers demonstrate that negative bias temperature instability (NBTI) affects static noise margin of SRAM cells. However, SRAM blocks may not only be affected by transistor aging, it is possible that some interconnects may become faulty over time. Manuscript received June 13, 2015; revised October 8, 2015; accepted November 8, 2015. Date of publication December 17, 2015; date of current version May 20, 2016. This work was supported in part by the Division of Computing and Communication Foundations through the National Sci- ence Foundation under Grant 1115663 and in part by the Microelectronics Advanced Research Corporation under Grant 2198.001. The authors are with the Department of Electrical and Computer Engineer- ing, University of California at Santa Barbara, Santa Barbara, CA 93106 USA (e-mail: zhong@ece.ucsb.edu; mms@ece.ucsb.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2015.2501900 Electromigration (EM) is one of the major failure mecha- nisms that limit the long-term reliability of interconnects [4]. In modern technologies, EM not only affects the power and ground (P/G) lines [5] but it may also damage signal lines [6]. It is well known that short signal lines that carry bidirectional currents are relatively EM resistant and their time to failure (TTF) is rather long. However, SRAM arrays include bitlines which are long signal lines that carry mostly unidirectional currents [6]. These lines over time may be damaged by EM. This is the focus of this paper. Current flows on a bitline during both write and read operations. The write currents are mostly balanced and do not contribute to EM. When a read operation is performed, the bitline is charged by the same pMOS transistor placed at one end and discharged by an SRAM cell placed elsewhere within the bitline range, leading to a unidirectional current path. The subthreshold leakage current has a similar path. Since the current of read operation is a dominant component, it is possible that bitlines may be affected by EM [6]–[8]. The leakage current of a bitline consists of subthreshold leakage current from all SRAM cells connected to the bitline and its value is greatly affected by the threshold voltage and channel length of each bitline access transistor. The current density of the bitline, closely related to the lifetime of EM, is also affected by the actual width of the line, which suggests that the variation of bitline width also needs to be considered. All these facts imply that process variation may degrade bitline EM reliability and should be modeled in EM failure analysis. Threshold voltage variation, mainly caused by random dopant fluctuation, can be approximated by Gaussian distribution if there are enough dopants in the channel region [9]–[11]. Transistors with low threshold voltage may still work properly. However, the leakage current of such transistors may dramat- ically be increased as dictated by the typical subthreshold slope (70–90 mV/decade). In modern technologies, the one sigma variance of the transistor threshold voltage is already exceeding 20% of the nominal value (57 mV for 22-nm tech- nology), according to the international technology roadmap for semiconductors report [12]. Thus, the subthreshold leakage current of an SRAM cell can easily be 1000 times greater than its nominal value for a transistor with four-sigma threshold value. Such a statistical event is very likely to happen in an SRAM array due to a large number of cells. Hence, the threshold voltage variation, originally believed to cause a 1063-8210 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.