Active Backplane Design for Digital Video Walls Douglas R. Dykaar 1 , Roohollah Samadzadeh Tarighat 2 , Feng Chen 3 , Tyler Davidson-Hall 2 , Graham Hill 3 , John Vieth 3 , Chris Brown 3 , Hany Aziz 2 , and Siva Sivoththaman 2 1. DifTek Lasers, Inc., Waterloo Canada 2. Department of Electrical & Computer Engineering, University of Waterloo, Waterloo Canada 3. Christie Digital Systems Canada Inc., Kitchener Canada ABSTRACT We report on the design of a scalable active backplane for digitally driven video wall displays. The substrates use single- crystal silicon spheres which are embedded in ceramic and planarized. Author Keywords Digital-Signage Display Solutions, Display Materials and Processes, single crystal silicon, transistor, backplane, active matrix, display electronics, LED, OLED. 1. OBJECTIVE AND BACKGROUND In this paper a scalable manufacturing process for high performance digital video walls is presented. While the process uses mostly standard Si technology, there are several key features that are required due to the use of randomly oriented Si spheres as substrates embedded in a ceramic matrix. From a device standpoint, the mobility of any type of amorphous or poly-crystalline thin-film transistor (including non-Si and organic devices) is much smaller than single-crystal Si transistors. Electron mobility in amorphous Si is ~1 cm 2 /V·s compared to ~100 cm 2 /V·s for poly-Si, and ~1500 cm 2 /V·s for high-quality single-crystal Si. It is therefore advantageous to use single-crystal Si in place of amorphous Si in such devices. By embedding Single Crystal Silicon (SCS) spheres in ceramic substrates and planarizing the surface, large area substrates with high mobility silicon can be realized. These substrates offer a high performance to cost ratio. For p-type spheres, bulk hole mobility of 400 cm 2 /V·s has been achieved [1], electron mobility for field effect transistors on a Si wafer using a scalable process of > 500 cm 2 /V·s has been realized [2] and device mobility of > 300 cm 2 /V·s has been measured on planarized SCS spheres [3]. The process is generally a standard Si process with some exceptions. Silicon nitride layers are deposited as the gate dielectric instead of thermally grown oxides. This is due to the strong crystallographic dependence of gate oxide growth rate [4] which could lead to performance variation when applied to randomly oriented surfaces of the planarized silicon spheres. Thermal diffusion of dopants is used, rather than ion implantation for formation of the doped regions, because of the lower cost and scalability advantage of the diffusion process. In addition to scalability, high performance and low cost, the active substrates can also be configured to accommodate Surface Mount Devices (SMD), such as RGB LEDs. The LTCC ceramic substrate is similar to substrates now used to package RGB LEDs, so the individual LED die mounted inside the SMD package could also be mounted directly on the substrates used here, resulting in tiles directly, as opposed to individual RGB pixels. The same backplane design can be used with OLED emitters, either fabricated conventionally on top of the backplane, or on a separate substrate and subsequently attached to the active backplane. 2. SUBSTRATE DESIGN Commercial Low Temperature Co-fired Ceramic (LTCC) (DuPont 951) was used. In the as-cast state, the sheets are flexible and can be easily punched. The top layer has holes punched in predetermined locations for sphere embedment. An additional layer laminated to the back provides additional mechanical rigidity, and blind holes to set spheres into and a smooth backside for ease of vacuum handling. Figure 1 shows an image of a three layer, 8” LTCC stack after firing. The pitch for the holes is 3 mm and the circular shape is chosen to be used for device fabrication using the standard tools for silicon wafer processing available in the lab. For this trial a small pattern is repeated four times. A ~5.5” square shape can be cut from the 8” substrate. Larger sheets are readily cast in the green phase. Figure 2 shows a schematic cross section for (a) an LED wall tile and (b) a flipped OLED bottom emitter array made up of an Figure 1. A three layer 8” diameter stack of LTCC sheets after firing. The top layer has holes in predetermined locations which are used to locate the silicon spheres. The shape is circular to allow the use of available silicon wafer processing tools.