Microelectronics Reliability 76-77 (2017) 68–74 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel Method for evaluation of transient-fault detection techniques R.A. Camponogara Viera a, b, c , 1 , R. Possamai Bastos a, * , J.-M. Dutertre b , P. Maurine c , R. Iga Jadue a a Univ. Grenoble Alpes, CNRS, TIMA, Grenoble, France b IMT Mines Saint-Etienne, Centre CMP, Equipe Commune CEA Tech - Mines Saint-Etienne, F-13541 Gardanne, France c LIRMM, CNRS, UMR N5506, Montpellier, France ARTICLE INFO Article history: Received 19 May 2017 Received in revised form 1 July 2017 Accepted 2 July 2017 Available online 12 July 2017 Keywords: Transient fault Concurrent error detection Fault detection Transient-fault detection ABSTRACT This work introduces a simulation-based method for evaluating the efficiency of detection techniques in identifying transient faults provoked in combinational logic blocks. Typical fault profiles are simulated in campaigns of injections that reproduce output scenarios of fault-affected combinational circuits. Further- more, a detection technique is proposed and compared to state-of-the-art strategies by using the method presented herein. Results show the capabilities of all studied techniques, providing a rank in terms of their efficiencies in detecting transient faults induced in combinational logic circuits, and analyzing the situations in which soft errors are produced in memory elements. © 2017 Elsevier Ltd. All rights reserved. 1. Introduction With the downscale of integrated circuits components, increas- ing their robustness against various natural or human aggressions is becoming a challenging task. Among natural aggressions, one can identify aging or environmental radiations [1]. Among human aggressions one can cite fault injection to the end of disabling embedded security protocols or mechanisms [2]. Several phenomena such as radiation exposure and many others caused by environ- mental conditions are able to induce parasitic transient currents in integrated circuits. Intentional sources, such as laser beams can also be used, since it allows finely controlling the injected transient faults thanks to the high spatial and temporal resolutions of laser shots [3]. Transient faults (TFs) are active only for a short duration of time and their occurrence are not predictable when caused by the envi- ronment. Therefore, TFs must be detected and corrected at runtime before becoming a soft error (SE) that may affect the operation of the target. Error detection during circuit normal operation is typically called concurrent error detection (CED) [4]. Several CED techniques have been proposed with the intent to design reliable computing systems [5–13]. These techniques mainly * Corresponding author. E-mail address: bastos@univ-grenoble-alpes.fr (R.P. Bastos). 1 CNPq - Ph.D. Fellowship Program. differ in their detection capabilities and in the constraints they impose on the system design. This paper presents a simulation-based method to evaluate and compare different detection techniques regarding their efficiency in detecting TFs arisen in combinational logic blocks and result- ing in soft errors. The method proposes 32 different scenarios of TF injection. Results of all detection techniques studied here are sum- marized in a table that provides a direct insight of the efficiency of each technique. Furthermore, in this paper, another CED tech- nique is introduced and compared among the other techniques. It uses an efficient transition detector (TD) and a controllable adap- tive detection window (DW). As a result, the introduced technique offers increased SE detection capability but also allows the detection of delay errors (DEs). 2. Techniques for concurrent error detection The CED techniques presented in this section can be clus- tered in three categories: spatial redundancy, temporal redundancy, and techniques based on the integration of a transition detector. Although these approaches can be implemented at different abstrac- tion levels of the design flow, this work considers only the hardware (transistor) abstraction level. http://dx.doi.org/10.1016/j.microrel.2017.07.007 0026-2714/© 2017 Elsevier Ltd. All rights reserved.