Rajendra Bahadur Singh Dept. of Electronics & Comm., School of ICT Gautam Buddha University, Greater Noida, INDIA rbs2006vlsi@gmail.com Anurag Singh Baghel Dept. of Computer Science, School of ICT Gautam Buddha University, Greater Noida, INDIA asb@gbu.ac.in ! " " # $% & ! " ’ " () ) " *" I. INTRODUCTION Floorplanning[1.3] is an essential design step of VLSI physical design automation[4]. It determines the size, shape, and locations of modules in a chip and as such, it estimates the total chip area, interconnects, and, delays. Computationally, it is an NP.hard problem; researchers have suggested various heuristics and metaheuristic algorithms solve it. A primary research problem in the VLSI floorplanning[12] is its representation. The representation of Floorplan determines the size of search space and the complexity of the transformation between a representation and its corresponding floorplan. Floorplanning is defined as the process of placing circuit blocks to a given 2D boundary. It is a very crucial step in the VLSI physical design, and the quality of floorplanning significantly affects the successive design steps such as placement and routing. In the early days, floorplanning was tractable since the sizes of chips were limited and designers were able to generate desirable floorplans manually. But in recent years the complexity of design become larger and the number of modules also increased so modern floorplan design becomes impossible manually. Computationally, it is an NP.hard problem [21]; researchers have suggested various heuristics and metaheuristic algorithms solve it. A primary research problem in the VLSI floorplanning is its representation. The representation of floorplan determines the size of search space and the complexity of the transformation between a representation and its corresponding floorplan. From the complexity point of view, it is an NP.hard problem. The search space increases exponentially with the increase in the number of modules therefore to get an optimum solution is an outdaring task. The quality of floorplanning depends on how it is represented. The representations of floorplans determine the size of the search space and the complexity of transformation between its representation and its corresponding floorplan. There are various representation methods for floorplan such as Bounded Sliced Grid (BSG)[11], Corner Block International Journal of Computer Science and Information Security (IJCSIS), Vol. 16, No. 4, April 2018 117 https://sites.google.com/site/ijcsis/ ISSN 1947-5500