IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 8, Issue 1, Ver. I (Jan.-Feb. 2018), PP 47-59 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 www.iosrjournals.org DOI: 10.9790/4200-0801014759 www.iosrjournals.org 47 | Page Basic Topologies of MOS Single-Stage Amplifiers. DC Analysis For Maximum Input-Voltage Swing And Amplification George P. Patsis 1,2 1 Department of Electronic Engineering,Technological and Educational Institute of Athens,Aegaleo, Attica, Greece 2 Nanometrisis private company, Scientific & Technological Park "Leukippos", NCSR Demokritos, Neapoleos 27 &Patr. Grigoriou Str., 15341, AgiaParaskevi, Attica, Greece Corresponding Author:George P. Patsis Abstract: Review basic MOS single-stage amplifier topologies and perform comparative DC analysis in order to determine for each topology the pair: (maximum input voltage swing, amplification). The results will be used in following works for the design of more advanced circuits such as differential amplifiers, current sources and operational amplifiers. Keywords: integrated analog design, single-stage amplifier, dc-analysis, voltage-swing, amplification --------------------------------------------------------------------------------------------------------------------------------------- Date of Submission: 15-02-2018 Date of acceptance: 01-03-2018 --------------------------------------------------------------------------------------------------------------------------------------- I. Introduction The aim of the current work is to give a didactic review to the design of the most basic MOS single-stage amplifiers [1,2]. The aim is on creating appropriate single-stage amplifier designs delivering maximum input voltage swing and maximum amplification. (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) Figure 1. MOS single stage topologies. (a) Common-source stage with resistive load, (b) Common-source stage with diode-connected load, (c) Common-source stage with current-source load, (d) Common-source stage with active load, (e) Common-source stage with triode load, (f) Common-source stage with source degeneration, (g) Source follower, (h) Source-follower with nMOS as current source, (i) Common-gate stage, (j) Cascode-stage, (k) Simple folded cascode, (l) Simple folded cascode with nMOS input. V in V DD R D V out M1 V in V DD M 2 V out M 1 V DD V b V in V out M1 M2 V DD V in V out M1 M2 V DD V b V in V out M1 M2 V in M 1 V out R S R D V DD V in M 1 V out R S V DD V DD V in V out M1 V b M2 V b R D V DD V out M1 V in M1 M2 R D V DD V out V b V in V DD V in R D V b M1 M2 V out V in M1 R D M2 V b V out V DD