IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 8, Issue 2, Ver. I (Mar.-Apr. 2018), PP 58-64 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 www.iosrjournals.org DOI: 10.9790/4200-0802015864 www.iosrjournals.org 58 | Page Retime Low Power Approximate Multiplier for Image Sharpening and Smoothing Jalaja S 1 , Tejaswini A 2 VTU Research Scholar, Assistant Professor Department of ECE, BIT, Bangalore, India M. Tech, Department of ECE, BIT, Bangalore, India Corresponding Author: Jalaja S Abstract: In DSP systems, due to demand in the higher computational performance in the architecture’s is increasing the complexity. In order to enhance the performance, the approximate arithmetic circuits are designed with small errors to increase the speed. The main aim of this work is to approximate the multiplication process with low power consumption. In this paper, a retime low power approximate multiplier is proposed. The approach is based on rounding the operands to the nearest exponent of two. Using this approach, the computational intensive part of multiplication is omitted and thus improving the speed of the multiplier at the cost of small penalty errors. This proposed approach is appropriate for both signed and unsigned operations. The efficiency of the proposed Retime approximate multiplier is analyzed by FIR filter using cross correlation method in image sharpening and smoothing. Key Words: Approximate Multiplier, Retime Rounding number, Finite Impulse Response (FIR) --------------------------------------------------------------------------------------------------------------------------------------- Date of Submission: 25-04-2018 Date of acceptance: 14-05-2018 --------------------------------------------------------------------------------------------------------------------------------------- I. Introduction In any electronic systems, Energy minimization is one of the most important design requirements, especially in the portable ones such as smart phones, tablets and different gadgets. It is greatly desired to reach this minimization with minimal performance (speed) penalty [1]. Digital Signal processing (DSP) blocks are core components of these portable devices for performing various multimedia applications. The computational core of these DSP blocks is the arithmetic logic unit (ALU) where multiplications and additions have the more share among allother arithmetic operations [2]. The multiplications play leading operation in the processing elements which can leads to high consumption of energy and power. Thus, improving the speed and power/energy-efficiency characteristics of multipliers plays an important role in improving the efficiency of processors. Soo many DSP cores implement image and video processing algorithms where end results are either images or videos prepared for human use. This feature enables us to use approximations for improving the speed/energy efficiency. This arises from the limited perceptual abilities of human beings in observing an image or a video. Apart from these image and video processing applications, there are other areas where the exactness of the arithmetic operations is not important to the functionality of the system (see [3], [4]). Due to the use of approximate computing provides the designer with tradeoffs between the accuracy and the speed and also the power/energy consumption [2], [5]. At different design abstraction levels like circuit, logic and architecture levels as well as algorithm and software layers this approximation can be applied [2]. The approximation may be performed using different methods such as enabling some timing violations (e.g., voltage overscaling or overclocking) and function approximation methods (e.g., modifying the Boolean function of a circuit) or a combining both the methods [4], [5]. In the function approximation methods, several approximating arithmetic building blocks, like adders and multipliers, at different design levels have been recommended (see [6]– [8]). In VLSI Signal Processing there are two types of digital filters i.e. FIR (finite impulse response) and IIR (infinite impulse response). FIR is that the impulses are finite in this filter and phase is kept linear in order to noise distortions and no feedback is used for such filters. FIR is very easy to design when compared with IIR. These FIR filters are used in DSP processors for high speed. The FIR filter is used to check the efficiency of image processing applications. In this paper, we focus on proposing a Retime low power approximate multiplier appropriate for errortolerance DSP applications. The main contributions of this paper can be outlined as follows: