International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 04 | Apr-2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 6.171 | ISO 9001:2008 Certified Journal | Page 1108 Review on the dual use of Power line - A CMOS Receiver Design Khushboo Shukla 1 , Anshuj Jain 2 , Bharati Chourasia 3 1 M.Tech Scholar [VLSI], Department of EC, Scope College of Engineering Bhopal, 2 GUIDE, AP Department of EC, Scope College of Engineering Bhopal, 3 3 HOD of EC department, Scope College of Engineering, Bhopal ---------------------------------------------------------------------***--------------------------------------------------------------------- Abstract - Today there are many designs are available for a CMOS receiver. Not only their effectively work and circuit complexity increases. They also proportionally increase the number of internal nodes, and individual internal nodes are less accessible due to the limited number of I/O pins present in the PDN. To overcome all the problems, author suggested power line communications (PLCs) at the chip of the circuit, specifically the dual use of power lines of the chip and power distribution networks for the application and the observation of test data and the delivery of power. In this paper we explain and proposed the PLC receiver the transmission of data through power lines. The main objective of the suggested PLC receiver is the robust operation under variations and droops of the supply voltage rather than high data speed. The suggested PLC receiver is going to design with the 0.18 um CMOS design technology under the supply voltage 1.8 V. Key Words: Design-for-testability (DFT), PLC at ICs, NMOS Design, PLC receiver, power line communications (PLCs). 1. INTRODUCTION As the new generation of deep sub micrometer VLSI technologies, testing, debugging, and diagnosis of VLSI circuits become more difficult and expensive. In virtue of higher circuit complexity for this technology, larger process variations, larger interconnection delays relative to transistor switching time, larger leakage current makes the testing more challenging. It is a general consent among test engineers that accessibility, i.e., controllability and observability, to internal nodes for both 2-D and 3-D ICs is essential to address the testing problems. As the circuit complexity increases simultaneously the number of internal nodes increases, and individual internal nodes are less accessible due to the limited number of available I/O pins. According to our knowledge best approach to provide ubiquitous accessibility to internal nodes is the dual use of power pins and power distribution networks (PDNs) for data communications as well as power supply. The PLC at the IC level would be useful for low data rate communications such as scan design, system debugging, and fault diagnosis. The approach also eliminates the need to route a data path from the node to an external data pin. 2. LITERATURE REVIEW In this paper[1] the proposed power line communications (PLCs) at the IC level, basically the dual use of power pins and PDN for application and observation of test and also delivery of power. A PLC receiver presented in this paper intends to demonstrate the proof of concept, mainly the transmission of data through power lines. The special concern of this receiver is to achieve the robust operation under the applied voltage and the variations in the supply. The PLC receiver is designed and fabricated in CMOS 0.18- μm technology under a supply voltage of 1.8 V. The results of the receiver can tolerate a voltage drop of up to 0.423 V for a data rate of 10 Mb/s. The power dissipation of the receiver is 3.26 mW and the core area of the receiver is 74.9 μm × 72.2 μm. This paper [2] proposes a various signaling method for efficient scanning based on the dual use of power lines. The preferred signaling scheme to increase the channel capacity for the multiple parallel scan design, and suggested adoption of the UWB (Ultra Wideband) and direct sequence - code division multiple access (DSCDMA) communication technologies. Because of the wide bandwidth, a UWB signal can reduce its average power level practically to the noise level. The DS-CDMA further mitigates the noise and allows multiple scan inputs to share the connectivity power lines. We studied the feasibility of the proposed scheme through SPICE tool and show the simulation results. In this analysis [4] speed or even faster speed testing of VLSI circuits aims for high-quality checking of the circuits through testing the performance of related faults. On one side, a compact test set with highly effective to checking the each and every delay faults and also desirable for lower test costs. On the other side, this process increases switching activity during launch and capture operations. This process enhance the quality and cost may thus end up violating peak-power constraints which shows the yield loss, while working on this process generation of pattern under less switching constraints may lead to loss in test quality as well as pattern count inflation. In this paper, they given the design for testability (DfT) support for enabling the use of a set of patterns optimized for cost and quality as is, yet in a low power manner; they developed three different DfT mechanisms,(1) launch-off shift,(2) launch-off capture, and (3) mixed at-speed testing. The given DfT support enables a design partitioning approach, where any given set of patterns, generated in a power-unaware manner, it can be used to test the design regions one by one, it reduces both launch and capture power in a design-flow compatible manner. This is the way to the test pattern count and quality, while lowering the launch/capture power.