SENSOR ANALOG FRONT-END ADC PROCESSOR TRANSCEIVER MEMORY POWER UNIT Fig. 1. Typical diagram of wireless mote. High Performance Digital Subthreshold Logic Daniel Orradre, M. Pilar Garde and Antonio Lopez-Martin Dept. Electrical and Electronic Eng. Public University of Navarra Pamplona, Spain antonio.lopez@unavarra.es Jaime Ramírez-Angulo Klipsch School of Electrical and Computer Engineering New Mexico State University Las Cruces, NM, USA jairamir @nmsu.edu Ramón G. Carvajal Dept. of Electronic Engineering University of Seville Sevilla, Spain carvajal@us.es Abstract—A new CMOS digital logic family operating with supply voltage below the threshold voltage is presented. It is based on the use of Quasi-Floating Gate transistors, allowing ultra-low voltage operation without the strong performance degradation of former subthreshold approaches. Measurement results of a CMOS test chip prototype are included, validating in practice the proposed techniques. Keywords— Ultra Low Voltage Design; Quasi-Floating Gate Transistor; CMOS Digital Logic. I. INTRODUCTION Several applications currently demand ultra-low energy consumption. Among them, energetically autonomous wireless sensor networks employing energy harvesting techniques are a relevant example. These networks are among the most promising technologies in the near future. They allow the deployment of a large number of energy-autonomous wireless microsensor nodes in an ad-hoc configuration, which interact enabling distributed monitoring and actuation. A variety of application scenarios are envisaged for these networks in the fields of healthcare, environment monitoring, energy efficiency in buildings, agriculture, industrial control, antomotive systems, military surveillance, planetary exploration, seismic activity monitoring, fire detection in forests, etc. Typically, microsensor nodes arranged in ad-hoc topologies benefit from spatial diversity through multi-hop communications and exploit spatial correlation through data fusion. Figure 1 shows a typical microsensor node. It includes an analog front-end that processes the signal acquired from the sensor(s) (temperature or humidity sensor, electrode, etc.). Then an Analog to Digital Converter (ADC) converts the acquired signal to digital form. Subsequently, signal is processed and stored as required and it can be sent by the transceiver unit. The power unit draws energy from the power source (battery, solar cell, piezoelectric transducer, thermoelectric generator, antenna, etc.) and conditions it properly to supply the different modules of the system. If the microsensor node needs to be energy-autonomous, it has to be powered by an energy harvesting source. In this case the battery (or alternatively, a super-capacitor) is only used for temporary storage of the energy harvested. This places highly demanding requirements in terms of energy to the microsensor circuits. In particular, this paper focuses on the design of the digital circuits for such autonomous microsensor nodes and for ultra low voltage applications in general. Making these microsensor nodes operate with the minute energy harvested from the environment is a challenging task. A key goal to minimize energy consumption is reducing the supply voltage. However, conventional operation of CMOS transistors requires supply voltages above the threshold voltage of these devices. A groundbreaking advancement was the proposal of subthreshold operation in 1972 [1]. Since then, several analog subthreshold circuits were developed for low- power applications (e.g. [2], [3]). However, digital subthreshold circuits did not receive the same interest until the late 1990s [4], [5], [6]. These proposals often use body biasing and suffer from strong performance degradation as a consequence of the severe supply voltage reduction. The delay of the circuits increases exponentially with the reduction of supply voltage, and the leakage becomes very relevant [7]. In this paper, we propose an alternative approach to achieve subthreshold digital circuits based on Quasi-Floating Gate (QFG) transistors [8]. The paper is organized as follows. Section II summarizes the operation of QFG transistors. The proposed subthreshold CMOS logic family is described in Section III. Simulation and measurement results that validate the proposed ideas are presented in Section IV. The main conclusions are drawn in Section V. II. QFG MOS TRANSISTOR The layout and equivalent circuit of a 2-input QFG MOS transistor is shown in Figs. 2(a) and 2(b), respectively. The gate is weakly connected to a proper DC voltage using a large- valued resistor which can be implemented by the leakage This work has been supported by the Spanish Ministerio de Economía y Competitividad, grant TEC2010-21563-C02-01/MIC.