Low Power Network-on-Chip Virtual Channel Router Architecture A.Kalimuthu, Dr.M.Karthikeyan Department of ECE, JCT college of Engineering and Technology, Principal, Tamilnadu College of Engineering Kalimuthu.a@jct.ac.in Abstract—Nowadays Network on Chip (NoC) is employed rather than System on Chips (SoCs) for better performance. Because of shrinking technology sizes, more and more processing elements (PEs) and memory blocks are increasingly being integrated on a single chip. But, conventional communication infrastructures can’t manage the synchronization issues of the large systems. Using NoCs is a step towards solving that communication problem. For NoC architecture, good performance effective routing algorithms with low power utilization are crucial for real-time applications. In the proposed, we present a novel systematic approach for the router utilizes the concept of acyclic sorting operation which replaces the cyclic round robin arbitration to obtain a low power network on chip router architecture and this architecture is described in detail in this paper. This design achieves reduce the area and decrease in power. Keywords—Network on Chip, router, Bmax unit, Marx unit. I. INTRODUCTION Since the introduction of research into multi-core chips in the late 1990s [1], on-chip networks have emerged as an important and growing field of research. As core counts increase, and multi-core processors emerge in diverse domains ranging from high end servers to Smartphone's and even Internet of Things (IoT) gateways, there is a corresponding increase in bandwidth demand to facilitate high core utilization and a critical need for scalable on-chip interconnection fabrics. This diversity of application platforms has led to research in on-chip networks spanning a variety of disciplines from computer architecture to computer-aided design, embedded systems, VLSI, and more. Here, we provide a synthesis of critical concepts in on-chip networks to quickly bootstrap students and designers into exciting field [2]. In the new computer era, where the design perspective to increase computing performance moves from increasing working frequency of a single core processor system to increasing the number of working processors in a multi-core processor system, the NoC will become a preferred communication infrastructure, when the number of cores will be more than ten cores. A sophisticated communication structure is needed for the inter-processor data exchanges. NoC came into existence primarily to replace the traditional shared bus networks with wires of shorter lengths which can drastically improve the feasibility and flexibility of the complete system [3]. NoC is basically a packet-based interconnection network, but the flow of data is in flits. Each packet consists of a head flit and body flit where the former has the details of source and destination address and the latter contains the actual data to be transmitted. The significance of NoC [4] is that it can simplify the hardware that controls the routing and switching functions. Routers [5] and Network Interfaces (NIs) form the basic composition of a typical NoC. The hub of any on-chip network is a router [6] which is categorized functionally into two regimes namely i) Data path and ii) Control Logic. The former constitutes the switch fabric and the latter controls the data flow i.e. the switching [7] of packets from one router to the other or to the NI. The architecture of the router [8] must be kept as simple as possible to reduce area, power and improve speed. This paper presents a new architecture for router which is of less complexity and consumes lower power. Shield is a reliable router architecture which can be tailored with respect to the parameters area, power and delay. The proposed router is a NoC Virtual Channel router consisting of five input and five output ports. Each input port in turn consists of 3 Virtual Channels (buffers). The foundational blocks in the proposed router are Routing Computation Unit, Virtual Channel Allocator Unit, Integrated Switch Allocator and Crossbar Unit and these will be explained in detail in the succeeding section. Organization of the remaining of the paper is given below. Section II presents a glimpse of Literature Survey referred for this design. Section III describes the complete design of proposed router. Section IV provides the experimental outcomes. Section V concludes this paper. II. RELATED WORK Router architecture known for its good reliability [9], [10], [11]. It is more reliable when compared with the baseline router with respect to hard faults. Due to Silicon Protection Factor, it is reliable when evaluated with respect to other router architectures which have the quality of fault tolerance. The results of Shield [11] show that it has 34% and 31% increase in area and power respectively when evaluated with the baseline router. In a nutshell, Shield balances between reliability and the overhead. The switch allocator is used to provide access for flits to the input ports of crossbar and the crossbar is the switch fabric between input International Journal of Scientific Research and Review Volume 7, Issue 6, 2018 ISSN NO: 2279-543X http://dynamicpublisher.org/ 749