Hitansu Sekhar Sahu Journal of Engineering Research and Application www.ijera.com ISSN : 2248-9622, Vol. 8, Issue5 (Part -IV) May 2018, pp 73-77 www.ijera.com DOI: 10.9790/9622-0805047377 73 | Page Design And Implementation Of High Speed Vedic Multiplier Hitansu Sekhar Sahu 1 , Khirod Kumar Sethi 2 , Tejesh Kumar Chaudhary 3 , Hemant Kumar Besra 4 , Prasanta Kumar Parida 5 , Subha Ranjan Sahoo 6 , Abhinash Kumar Pala 7 1,2,3,4,5,6,7 (Depart. Of Electronics And Telecommunication Engineering, Parala Maharaja Engineering College, Berhampur, Odisha (India) Corresponding Auther: Hitansu Sekhar Sahu ABSTRACT Vedic mathematics is the ancient Indian system of mathematics. This paper proposed the design oh high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that has been modified to improve performance. Multipliers play a major role in processors and in many computational systems. The speed of these systems greatly depends on the speed of its multipliers. In order to enhance the speed of the systems the faster and efficient multipliers should be employed. Vedic Multiplier is one of the best solution which is capable of performing the quicker multiplications by eliminating the unwanted steps in the multiplication process. Vedic Multiplier deals with a total of sixteen sutras or algorithms for predominantly logical operations. In this paper it is used for designing a high speed, low power 4X4 multiplier. In the proposed design we have reduced the number of logic levels, thus reducing the logic delay. The proposed system is design using VHDL and it is implemented through Xilinx 8.1. Keywords – Urdhva Tiryakbhyam Sutra, Vedic Mathematics, Vedic Multiplier --------------------------------------------------------------------------------------------------------------------------- Date of Submission: 07-05-2018 Date of acceptance: 22-05-2018 --------------------------------------------------------------------------------------------------------------------------- I. INTRODUCTION Veda is a Sanskrit word which means „Knowledge‟. Vedic Mathematics is the name given to the ancient system of Indian Mathematics which was rediscovered from the Vedas between 1911 and 1918 by Sri Bharati Krsna Tirthaji (1884-1960). Vedic Mathematics [6] is a collection of Techniques/Sutras to solve mathematical arithmetics in easy and faster way. It consists of 16 Sutras (Formulae) and 13 sub-sutras (Sub Formulae) which can be used for problems involved in arithmetic, algebra, geometry, calculus, conics. The maximum famous amongst those sixteen are Nikhilam Sutram [3], Urdhva Tiryakbhayam, and Anurupye. It has been found that Urdhva Tiryakbhayam is the maximum efficient among those. Urdhva Tiryagbhyam is the most generalised sutra for implementation of Vedic Multiplier designs because with increase in number of bits both area and delay increase slowly [5]. The beauty of Vedic Multiplier lies in the fact that they can be used to solve cumbersome mathematical operations orally thereby improving speed. Vedic Multiplier has become highly popular as a faster method for computation and analysis [4]. Multiplication [8] is the most important arithmetic operation in many applications such as Central Processing unit (CPU), MAC (Multiply and Accumulate) unit [2], Image Processors and Digital Signal Processors [1] etc. As speed is always a major requirement in the multiplication operation, increase in speed can be achieved by reducing the no. of steps in the computation process. In DSP system to perform operations such as Convolution, Discrete Wavelet Transform, Fast Fourier Transform, and Filtering etc multipliers are essential. The speed of the system is majorly depends on the multiplier unit. This is the one of the apt place for employed Vedic mathematics to perform multiplication. Multipliers being the key components of Arithmetic and logic units, Digital signal processing blocks and Multiplier and accumulate units, determine the performance and throughput of the applications. II. VEDIC MULTIPLICATIONS Urdhva tiryagbhyam sutra [9] is a general multiplication formula applicable to all cases of multiplication. RESEARCH ARTICLE OPEN ACCESS