A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template * Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, and J¨ urgen Teich Department of Computer Science 12, Hardware-Software-Co-Design, University of Erlangen-Nuremberg, Germany Abstract As modern areas of application for coarse-grained re- configurable systems digital signal processing, multime- dia in embedded devices, and wireless communication can be mentioned among others. These fields include dif- ferent algorithms with varying complexity and speed re- quirements. In this paper a new highly parameterizable coarse-grained reconfigurable architecture called weakly programmable processor array is discussed. It consists of several weakly programmable processing elements with a VLIW (Very Large Instruction Word) architecture which are connected with the help of dynamically reconfigurable in- terconnect modules. 1 Introduction Recent advances in the semiconductor technology allow the hardware designer to integrate several complex modules like processors, peripheral devices, and memory in a sin- gle System-on-a-Chip (SoC). A high level of reconfigura- bility and parallelism plays an increasingly important role in modern hardware systems. In particular, the embedded systems for digital signal processing have to be very flexi- ble and implement different signal processing standards at once. The embedded systems for wireless communication, for example, usually implement multiple wireless commu- nication protocols. Reconfigurable system architectures can be classified with the help of the single processing units functionality and the width and configurability of the interconnect [2,12]. The basis of the currently available fine-grained recon- figurable architectures build the so called lookup tables (LUTs), which can be configured to implement different logical functions. Lookup tables constitute together with an extremely flexible interconnect network with 1 bit granular- ity, see Fig. 1, such modern fine-grained reconfigurable ar- chitectures like Field Programmable Gate Arrays (FPGA). The high flexibility of the interconnect network has the dis- * Supported in part by the German Science Foundation (DFG) in project under contract TE 163/13-1. advantage to be very inefficient in terms of area usage. Up to 80 % of the total die area on a typical commercial FPGA is devoted to interconnect [11]. Another undesirable impact of the fine-grained interconnect schemes is that on the com- putational complexity of placement and routing algorithms, as well as the big reconfiguration data streams (up to sev- eral megabytes in modern FPGAs), and consequently long reconfiguration times [6]. Coarse-grained reconfigurable architectures are espe- cially suited to meet the demands on the computation re- sources, fast reconfigurability, and flexibility, as well as high power efficency for many reasons. Due to the big- ger widths of reconfigurable interconnect signals in coarse- grained architectures, see Fig. 2, much of the routing prob- lems are alleviated [6]. Furthermore, the amount of mem- ory to store different reconfiguration data streams is reduced and consequently the reconfiguration times of the coarse- grained architectures are much smaller. Complex compu- tations can be accomplished in the functional units of the coarse-grained architectures, since these can be complete processors with RISC architecture (Reduced Instruction Set Computer). The object of our research is a new class of massively parallel, reconfigurable, coarse-grained proces- sor architectures called weakly programmable processor ar- rays (WPPA). This paper is structured as follows: in Section 2 a brief overview of existing coarse-grained architectures is given. Section 3 contains the high-level architectural description of the class of weakly programmable processing elements and arrays we are introducing here. In Section 4 the con- figuration of weakly programmable processor arrays is dis- cussed. Section 5 gives an overview over the configuration data storage. In Section 6 experimental results are given. Finally, in Section 7 we give an outlook on further research subjects. 2 Related Work Many different academic and commercial coarse-grained reconfigurable architectures exist. A detailed overview of some of them can be found for example in [6]. Two well-