RF Characteristics and Mobility Performance of a 30nm Gate Length E-mode Junctionless Nanowire Transistor D.Sahoo Student member IEEE Member, IEEE Department of Electronics and Communication Engineering National Institute of Technology Silchar Silchar, Assam, 788010, E-mail:dibyadrastasomu@gmail.com Abstract-Junctionless Nanowire transistors are considered in the family of next generation high performance device group because of their simplicity in fabrication and very good scalable properties they provide. In this paper we report a 30nm Gate length non planar, ultra thin JNT for high frequency, high speed applications. We analyze the high frequency Microwave performance of the proposed device by successful variation in various high frequency parameters. The mobility performance is also discussed across thechannel of the device. Lastly, the electron transport phenomenon and alsothe energy band formation in the channel are also depicted in this paper. To the knowledge of the author the device discussed in this report is irst of its kind. Keywords-JNT,RF,Sten stabiliy factor,Electric ield,Mobiliy I. INTRODUCTION Over the past few years lunctionless Nanowire Transistors (JNT) have seen a lot of potential research.The next generation of lunctionless Nanowire Transistors are ultra scaled, high performance bulk plannar SOl structureshaving high carrier density at the channel.In this ever growing semiconductor industry these devices having CMOS unctionality made of Si nanowire ribbons are able to make a place for themselves. We discuss the device structure and its design considerations in Section II and Gate characteristics in Section III. The carrier transport phenomenon in the channel along with conduction band energy variationsare discussed in Section IV. The mobility performance and thehigh requency characteristics of this proposed device are discussed in Section V and VI respectively. Finally it is concluded in Section VII. II. DEVICE DESIGN CONSTDERATlON The proposed device structure consists of 30nm Schottky Gate over a Si0 2 layer having thickness tSj=20nm.A 40nm heavily doped Silicon layer is present under the dielectric which acts as the channel layer.The channel is present on the top of another Si0 2 undoped layer having 100nm thickness. This layer is sometimes known as'Box Layer'. The substrate is made upof Si having 8x10 18 cm, 3 p_type doping T. R. Lenka Student member IEEE Member, IEEE Department of Electronics and Communication Engineering National Institute of Technology Silchar IndiaSilchar, Assam, 788010, India E-mail:trlenka@gmail.com concentration.The n-type doping concentration used in the channel is of the order 1.67xl0 19 cm' 3 .As the channel doping in the proposed JNT is high due to overlap of energy band,it triggers tunnelling of electrons rom valence band of channel to conduction band of drain. The channel layer is also called 'Device Layer'having heavy n ++ doping and depleted in volume in the OFF state due to effective work unction difference with that of the Gate. Fig.l. Cross Section of ultra thinNT. The device structure used fordevice simulation using Atlas, Silvacois shown in Fig. l.The parameters used for simulating the device are enlisted in Table 1. TABLE 1 Parameters used in Simulation of the device Parameter Value (with unit) Channel doping 1.67x1019cm·3 N type) Channel length 30nm Buried oxide thickness 100nm Si Substrate doping 8xlOIs cm·3 (P type) Thickness of gate dielectric 20nm III. GATE CHARACTERISTICS The Gate characteristics of the device are portrayed in Fig. 2.The device displays a Vth of 0.98V which shows its enhancement type of behaviorand Sub threshold Swing of 107mV/decade.We also depict the logarithmic variations in