NOVATEUR PUBLICATIONS INTERNATIONAL JOURNAL OF INNOVATIONS IN ENGINEERING RESEARCH AND TECHNOLOGY [IJIERT] ISSN: 2394-3696 VOLUME 2, ISSUE 1 JAN-2015 1 | Page Design of carry save adder using transmission gate logic J.Princy Joice Dept of ECE/Sathyabama University, Chennai/Tamilnadu/India M.Anitha Dept of ECE/Sathyabama University, Chennai/Tamilnadu/India Mrs.I.Rexlin Sheeba Assistant Professor, Dept of ECE/Sathyabama University, Chennai/Tamilnadu/India ABSTRACT In this paper Carry Save Adder has been implemented. The comparison is done on the basis of two performances such as area, power consumption. The full adder cells for low power applications have been implemented using transmission gate based technique for sum and carry operation. In this paper transmission gate also used. It used to minimize the transistor count. By using the transmission gate the transistor count has decreased thereby the total chip area gets minimized and the power consumption also gets reduced. Keywords: Carry Save Adder, Full Adder, Power Consumption, and Transmission Gate. INTRODUCTION Most of the Very Large Scale IC (VLSI) applications, such as digital-signal processing and microprocessors, use arithmetic operations. In addition, among these widely used operations, subtraction and multiplication are most commonly used. The full adder is the building block of these operation modules. Therefore, enhancing its performance is crucial for ameliorating the performance of overall modules. Such an adder can be implemented using transmission gate technique. Among the logic styles available, transmission gate is found to enhance the circuit performance. Micro wind is a CMOS circuit editor and simulation tool for logic and layout-level design, running on Microsoft windows. It has been developed since 1998 through several versions, and is available as a freeware for educational purpose. In this paper, carry save adder based on transmission gate layouts are designed using Micro wind 2.7. TRANSMISSION GATE LOGIC The transmission gate is also known as pass gates represents another class of logic circuits which use TGs as basic building block. It consists of a PMOS and NMOS connected in parallel. Gate voltage applied to these gates is complementary of each other(C and Cbar). TGs act as bidirectional switch between two nodes A and B controlled by signal C. Gate of NMOS is connected to C and gate of PMOS is connected to Cbar(invert of c). When control signal C is high i.e. VDD, both transistor are on and provides a low resistance path between A and B. On the other hand, when C is low both are turned off and provide high impedance path between A and B. PASS TRANSISTOR LOGIC In PTL logic style gate and source propagates the signal. This logic style has a great functionality that can reduce the number of transistor counts. The pass transistor logic can be designed by either using pmos or nmos, but nmos is mostly desirable. This has low intermodal capacitance effects and therefore PTL enables low power and high speed digital circuits. Complementary pass transistor logic is pass transistor logic with complementary inputs and outputs. The pass transistors are used to design logic circuits. The pass transistor logic is used to minimize the chip area and power consumption of the circuit. EXISTING SYSTEM: With the Shannon’s theorem the sum and carry expressions are condensed and thereby the transistor count has decreased. In the existing design of full adder the carry was generated using three AND gates and one OR gate whereas