)nternational Research Journal of Engineering and Technology ȋ)RJETȌ e-)SSN: ʹ͵ͻͷ-ͲͲͷ͸ Volume: Ͳͷ )ssue: Ͳͺ | Aug ʹͲͳͺ www.irjet.net p-)SSN: ʹ͵ͻͷ-ͲͲ͹ʹ © 2018, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 128 A NOVEL LOW POWER AND LESS TRANSISTOR COUNT LEVEL TRANSLATOR USING 16nm CMOS TECHNOLOGY Ahmad Umar 1 , Anshuj Jain 2 , Balram Yadav 3 1 M.Tech Scholar [VLSI], Department of EC, Scope College of Engineering Bhopal, 2 GUIDE, AP Department of EC, Scope College of Engineering Bhopal, 3 HOD of EC department, Scope College of Engineering, Bhopal -------------------------------------------------------------------------***---------------------------------------------------------------------- - ABSTRACT: - In modern ICs design era many more circuits are design using CMOS because of lowest power consumption. The selections of designing of ICs in various ways i.e. multiple threshold voltage, small signal variations, network configuration etc. In this success with improving technology we are proposing a level translator which is designed and simulated on 16nm technology. In this work we have used modern technology 16nm FinFET is defining new design specification of level translator which shows 58ps delay and 207nW power consumption. Consequentially the energy per transition also reduce as 0.012fJ with the voltage range 0.25mV to 3.5mV and transistor counts is low using 12 transistor only.The frequency obtained in this work is 0.31GHz at 0.25 volt power supply.We have also calculated EDP for this work which is 0.7. Index Terms—Level translator, low power, low gate count, CMOS Technology. I INTRODUCTION In today’s System-on-Chip designs energy efficiency is one of the most important issues to address. Among the techniques known in the literature to reduce power dissipation, those based on power supply voltage reduction are considered very effective even though they can severely penalize speed performances [2]. Power consumption in CMOS circuits is proportional to the square of the supply voltage as well as supply current. Energy and Energy–delay product have become two of the most important design metrics in the current deep submicron technologies for the System–on–chip (CMOS) solutions and multi–core computing architectures for many common applications [4]. Therefore, it is a common practice to use separate supply voltages, in different parts of CMOSs and multi– core processors, in order to reduce the energy consumption [3]. in moderate-speed mixed signal circuits or in digital circuits where different blocks operate at different speeds, employing two or more different supply voltages is advantageous from the power dissipation viewpoint [5]. However, between the part of having a low supply voltage of VDDL and the other part of having a high supply voltage of VDDH, a voltage level translator is needed to convert the logic levels of (VSS, VDDL) to (VSS, VDDH) with minimum additional power dissipation and propagation delay [10]. (a) Level Translator Level translator is final stage use for shift the output DC level at the second stage down to about 0 volt to ground. It provide interfacing between the components that operate at different level maxim offer a wide range of high speed level, logic level smart card level translator in both unidirectional and bidirectional type. A level translator in digital electronic, also called a logic-level translator, is a circuit used to translate signals from one logic level translator or voltage domain to another. II. LITERATURE REVIEW Alexander Shapiro and E. by G. Friedman et. Al. Since the minimum feature size has shrunk beyond the sub-30-nm node, power density has become the major factor in modern microprocessors. Techniques such as dynamic voltage scaling operating down to near threshold voltage levels and supporting multiple voltage domains have become necessary to reduce dynamic as well as static power. A key component of these techniques is a level translator that serves different voltage domains. This level translator must be high speed and power efficient. The proposed level translator translates voltages ranging from 250 to 790 mV, and exhibits 42% shorter delay, 45% lower energy consumption, and 48% lower static power dissipation. In addition, the proposed level translator exhibits symmetric rise and fall transition times with up to 12% skew at the extreme conditions over the maximum range of voltages [1] Jos´e C. Garcia, and Juan A. Montiel–Nelson et. Al. had implemented on a 65nm CMOS technology they said that highly efficient CMOS level translator qc–level translator, under the large capacitive loading condition (2pF), qc–