Design and Characterization of Two Different Structure of Junctionless Nanowire Transistor Considering Quantum Ballistic Transport Model Md. Majharul Islam *† , Showmik Singha † , Md Mohsinur Rahman Adnan † , Tuhin Dev † † Dept. of Electrical and Electronic Engineering † Shahjalal University of Science and Technology, Sylhet-3114, Bangladesh * Email : majharul30@gmail.com Abstract— In this work, the performance of two different structure of double gate junctionless nanowire transistor (DG- JLNT) has been analyzed. The conventional junctionless double gate (JLDG) and the modified flared up source and drain with submerged gate electrode structure are analyzed using Non- Equilibrium Green’s Function (NEGF) approach by TCAD Silvaco Atlas. As the NEGF approach shows better accuracy than other approaches in quantum modeling simulation for smaller channel length, this work was conducted depending on this approach. Performance parameter named Drain Current (I D ), Threshold Voltage (V th ), Subthreshold Swing (SS), on state and off state current ratio (I on /I off ) for the mentioned structures of n-channel JLDG transistor are analyzed. Simulation has been performed by varying channel length (L g ) and oxide thickness (T ox ) to observe the electrical characteristics. In order to observe Short Channel Effects (SCEs), the above parameters were investigated. In essence, flared up JLNW transistor showed better SCEs performance in current on state and off state (I on /I off ) ratio and lesser Threshold Voltage Roll Off (TVRO) over channel length variation. But in other SCEs parameters like SS and Drain induced barrier lowering (DIBL), conventional JLDG is pictured as the better candidate. Index Terms— Junctionless nanowire transistor, Double-gate structure, NEGF, Flared up source and drain, Short Channel Effects, DIBL, I on /I off Ratio, Threshold Voltage Roll Off, Silvaco TCAD I. I NTRODUCTION According to Moore’s law, the modern trend is to scale down the size of transistors. To meet the challenge of the current market trend, the channel length of MOSFET is being reduced [1]. But reducing the gate length creates new challenges which are termed as Short Channel Effects (SCEs). For this reason, the compression of MOSFET is already a saturated area. To cope up with scaling challenge, a new type of transistor has been projected named “Junc- tionless Nanowire Transistor”. Junctionless transistors are variable resistors controlled by the gate electrodes [2]– [5]. In nanoscale regime, having junctions cause fabrication complexity, leakage currents, wastage of power, and over- heating to occur. So having no junction is advantageous. With the junctionless transistor, cheaper, and denser microchips become a possibility. The Junctionless Nanowire Transistor (JLNT) is a multi- gate device which operates in the similar principle to a conventional MOSFET device in spite of having no actual p-n junction in its structure [2]. The device was proposed in the recent past [3]. The transistors which are now existing are junction based most of the time. When the MOS devices Fig. 1. Schematic Diagram of JLDG Transistor Fig. 2. Schematic Diagram of Flared up JLDG Transistor enter into the nanoscale region, these p-n junctions require heavily doped density gradients. There arise different short channel effects (SCEs) which is one of the reasons for exploring JLNT [6]. For the laws of diffusion and the nature of statistically distributed atoms in the semiconductor device, ultra-shallow junctions formation with high doping concentration has become an increasingly herculean task for the industry of semiconductor. Novel techniques of doping and ultra speedy annealing techniques must be developed. To overcome these problems, the idea of JLNT is magical. Its normal operation mode is partial depletion without having any junction. The device having uniform doping reduces other source and drain engineering task which had been required to ensure density gradients in the channel, source, and drain region [7]. But in the double gate structure of JLNT, there is a problem of ensuring gate control over the channel. In this case, Flared Up JLNT can be a better candidate.